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PDF IR3082 Data sheet ( Hoja de datos )

Número de pieza IR3082
Descripción XPHASE AMD OPTERON/ATHLON 64 CONTROL IC
Fabricantes International Rectifier 
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No Preview Available ! IR3082 Hoja de datos, Descripción, Manual

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Data Sheet No. PD94710
IR3082
XPHASETM AMD OPTERONTM/ATHLON 64TM CONTROL IC
DESCRIPTION
The IR3082 Control IC combined with an IR XPhaseTM Phase IC provides a full featured and flexible way
to implement a complete Opteron or Athlon64 power solution. The “Control” IC provides overall system
control and interfaces with any number of “Phase ICs” which each drive and monitor a single phase of a
multiphase converter. With simple 5 bit voltage programming and a few external components, the IR3082
is also well suited for general purpose multiphase applications. The XPhaseTM architecture results in a
power supply that is smaller, less expensive, and easier to design while providing higher efficiency than
conventional approaches.
FEATURES
5 bit VID with 1% overall system set point accuracy
Programmable Dynamic VID Slew Rate
+/-300mV Differential Remote Sense
Programmable 150kHz to 1MHz oscillator
Programmable VID Offset and Load Line output impedance
Programmable Softstart
Programmable Hiccup Over-Current Protection with Delay to prevent false triggering
Simplified Power Good output provides indication of proper operation and avoids false triggering
Operates from 12V input with 9.75V Under-Voltage Lockout
7.0V/5mA Bias Regulator provides System Reference Voltage
Small thermally enhanced 20L MLPDQaptaaSckhaegeet4U.com
DataShee
APPLICATION CIRCUIT
12V
ENABLE
VID0
VID1
VID2
VID3
VID4
10 0.1uF
CDSSEL/
20 19 18 17 16
IR30821
2
VID0 NEABEL
VID1
GD
R
WP
DSSEL/
OUPT
MR
GNDL VCC
VBIAS
15
14
3 VID2 CONTROL EAOUT 13
IC4 VID3
FB 12
5
VID4 ONVSS-
CS
OR
DCVA
SET
OC
VDRP
NII
11
6 7 8 9 10
ORCS ROCSET
0.1uF
RVDRP
RVDAC
CVDAC
RVFB
DataSheet4U.com Page 1 of 1
POWER GOOD
5 Wire Analog Bus
(to PHASE ICs)
VCC SENSE
VSS SENSE
12/17/04
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1 page




IR3082 pdf
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IR3082
et4U.com
IR3082
+
"FAST"
VDAC
-
+
-
EAOUT
+
- ERROR
AMP
FB
RFB
ISOURCE
ISINK
VDAC
BUFFER
AMP
OCSET
VDAC
IOFFSET IROSC
IROSC IOCSET
CURRENT
SOURCE
GENERATOR
ROSC
BUFFER
AMP
+
-
ROSC
+
1.2V
-
VOSNS-
RVDAC
CVDAC
ROSC
SYSTEM
SET POINT
VOLTAGE
Figure 1 – System Set Point Test Circuit
PIN DESCRIPTION
PIN#
1-5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
PIN SYMBOL
VID4-0
VOSNS-
ROSC
VDAC
OCSET
IIN
VDRP
FB
EAOUT
VBIAS
VCC
LGND
RMPOUT
SS/DEL
PWRGD
ENABLE
PIN DESCRIPTION
Inputs to VID D to A Converter.
Remote Sense Input. Connect to ground at the Load.
Connect a resistor to VOSNS- to program oscillator frequency and OCSET, FB, and
VDAC bias currents.
Regulated voltage programmed by the VID inputs. Connect an external RC network
to VOSNS- to progDraamtaSDhyeneatm4Uic.cVoIDmslew rate and provide compensation for the
internal Buffer Amplifier.
Programs the hiccup over-current threshold through an external resistor tied to
VDAC and an internal current source. Over-current protection can be disabled by
connecting a resistor from this pin to VDAC to program the threshold higher than the
possible signal into the IIN pin from the Phase ICs but no greater than 5V (do not
float this pin as improper operation will occur).
Current Sense input from the Phase IC(s). If current feedback from the Phase ICs is
not required for implementing droop or over-current protection connect to the LGND
pin. To ensure proper operation do not float this pin.
Buffered IIN signal. Connect an external RC network to FB to program converter
output impedance.
Inverting input to the Error Amplifier. Converter output voltage is offset from the
VDAC voltage through an external resistor connected to the converter output voltage
at the load and an internal current source.
Output of the Error Amplifier.
6.8V/5mA Regulated output used as a system reference voltage for internal circuitry
and the Phase ICs.
Power Input for internal circuitry.
Local Ground for internal circuitry and IC substrate connection.
Oscillator Output voltage. Used by Phase ICs to program Phase Delay
Controls Converter Start-up and Over-Current Timing. Connect an external capacitor
to LGND to program.
Open Collector output that drives low during Start-Up and any external fault
condition. Connect external pull-up.
Enable Input. A logic low applied to this pin puts the IC into Fault mode. Do not float
this pin as the logic state will be undefined.
DataShee
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IR3082 arduino
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IR3082
IR3082 THEORY OF OPERATION
Block Diagram
The Block diagram of the IR3082 is shown in figure 7 and discussed in the following sections.
et4U.com
VCC
ENABLE
SS/DEL
VID4
VID3
VID2
VID1
VID0
VOSNS-
+
9.75V
9.0V
-
-
+
VCC UVLO
COMPARATOR
ENABLE
- COMPARATOR
+
0.225V
DISCHARGE
- + COMPARATOR
+
70mV
115mV
-
DELAY
COMPARATOR
-
+
+
+-
+
1.270V
VCHG
ON
1.205V
-
3.9V
-
OC
DISCHG
CURRENT
40uA
SS/DEL
IHICCUP
ON
DISCHARGE
IDISCHG
6uA
ICHG
OFF
-+
1.3V
66uA
+
SOFTSTART
- CLAMP
T
N
E
RR
ER
VU
OC
F
OF
=
D
I
V
700ns
BLANKING
FAULT
LATCH
S
SET DOMINANT
R
OC
COMPARATOR
+
-
VID INPUT
COMPARATORS
(1 OF 5
SHOWN)
+
1.24V
-
+
-
DIGITAL TO
ANALOG
CONVERTER
+ "FAST"
VDAC
+
ISOURCE
- ISINK
DataSheet-4U.com VDAC
BUFFER
AMP
IOCSETIROSC
-
+ VDRP
AMP
DISABLE
+
+
- ERROR
AMP
IFB
IROSC
PWRGD
VDRP
IIN
OCSET
EAOUT
FB
LGND
VDAC
DataShee
RMPOUT
ROSC
50%
DUTY
CYCLE
RAMP GENERATOR
IROSC
5.0V
VBIAS
1.0V
ROSC
BUFFER
AMP
+
-
CURRENT
SOURCE
GENERATOR
Figure 7 – IR3082 Block Diagram
VBIAS
REGULATOR
+
-
VBIAS
+
7.0V
-
VID Control
A 5-bit VID voltage compatible with AMD’s Opteron/Athlon64, as shown in Table 1, is available at the VDAC pin.
The VID pins require an external bias voltage and should not be floated. The VID input comparators, with 1.2V
reference, monitor the VID pins and control the 6 bit Digital-to-Analog Converter (DAC) whose output is sent to the
VDAC buffer amplifier. The output of the buffer amp is the VDAC pin. The VDAC voltage is trimmed to compensate
for the input offsets of the Error Amp to provide 1% system set-point accuracy and is pre-positioned 50mV higher
than Vout listed in Table1 for load positioning. The actual VDAC voltage does not determine the system accuracy
and has a wider tolerance.
The IR3082 can accept changes in the VID code while operating and vary the DAC voltage accordingly. The
sink/source capability of the VDAC buffer amp is programmed by the same external resistor that sets the oscillator
frequency. The slew rate of the voltage at the VDAC pin can be adjusted by an external capacitor between VDAC
pin and the VOSNS- pin. A resistor connected in series with this capacitor is required to compensate the VDAC
buffer amplifier. Digital VID transitions result in a smooth analog transition of the VDAC voltage and converter
output voltage minimizing inrush currents in the input and output capacitors and overshoot of the output voltage.
DataSheet4U.com Page 11 of 11
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