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Número de pieza | IR3094PBF | |
Descripción | 3 PHASE PWM CONTROLLER FOR POINT OF LOAD | |
Fabricantes | International Rectifier | |
Logotipo | ||
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Data Sheet No. PD 94716
IR3094PBF
3 PHASE PWM CONTROLLER FOR POINT OF LOAD
DESCRIPTION
The IR3094 Control IC provides a full featured, cost effective, single chip solution to offers a compact,
efficient solution for high current POL converters. Control and 3 Phase Gate Drive functions are integrated
into a single space-saving IC.
FEATURES
x 0.85V Reference Voltage
x 3A GATELX Pull Down Drive Capability
x Programmable 100KHz to 540KHz oscillator
x Programmable Voltage Positioning (can be disabled)
x Programmable Softstart
x Programmable Hiccup Over-Current Protection with Delay to prevent false triggering
x Simplified Powergood provides indication of proper operation and avoids false triggering
x Operates up to 16V converter input with 7.5V Under-Voltage Lockout
x 4.36V Under-Voltage Lockout threshold for gate driver voltage
x Adjustable Voltage, 150mA Bias Regulator provides MOSFET Drive Voltage
x Enable Input
x OVP Flag Output detects high side fet short at powerup
x Separate OVP sense line to sense the output voltage and latched OVP with protection
x Inductor DCR sensing for current seDnastianSghweiellts4uUp.pcoormt up to 5.1V output applications
x Available 48L MLPQ package
ORDERING INFORMATION
Device
IR3094MTRPBF
IR3094MPBF
Order Quantity
3000 per Reel
100 piece strips
PACKAGE INFORMATION
DataShee
NC
NC
ROSC
VOSNS-
OCSET
VREF
VDRP
FB
EAOUT
SS/DEL
SCOMP2
SCOMP3
IR3094
48LD MLPQ
GATEH1
PGND1
GATEL1
VCCL1_2
5VUVL
GATEL2
PGND2
GATEH2
VCCH2
VCCH3
GATEH3
PGND3
48L MLPQ
(7 x 7 mm Body)
JA = 27oC/W
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IR3094PBF
et4U.com
PARAMETER
BIASOUT Regulator
SETBIAS Bias Current
Set Point Accuracy
BIASOUT Dropout Voltage
BIASOUT Current Limit
Soft Start and Delay
SS/DEL to FB Input Offset
Voltage
Charge Current
Hiccup Discharge Current
OC Discharge Current
Charge/Discharge Current
Ratio
Charge Voltage
Delay Comparator Threshold
Discharge Comparator
Threshold
Over-Current Comparator
Input Offset Voltage
OCSET Bias Current
Max OCSET Set Point
Under-Voltage Lockout
VCC Start Threshold
VCC Stop Threshold
VCC Hysteresis
5VUVL Start Threshold
5VUVL Stop Threshold
5VUVL Hysteresis
PWRGD Output
Output Voltage
Leakage Current
TEST CONDITION
RROSC = 47k
V(SETBIAS)-V(BIASOUT) @ 100mA
I(BIASOUT)=100mA,Threshold when
V(SETBIAS)-V(BIASOUT)=0.45V
With FB = 0V, adjust V(SS/DEL) until
EAOUT drives high
Relative to Charge Voltage
DataSheet4U.com
V(OCSET)-V(VREF),
CSINM=CSINP1=CSINP2=CSINP3,
Note 1.
RROSC = 47k
Start – Stop
Start – Stop
I(PWRGD) = 4mA
V(PWRGD) = 5.5V
MIN TYP MAX UNIT
94 103 117.5 PA
0 0.25 0.55 V
1.2 1.8 2.5
V
150 250 500 mA
0.8 1.1 1.8
V
30 60 90 PA
3.5 6
9 PA
25 55 70 PA
9 10 13 PA/PA
3.8 4.0 4.2
V
180 245 310 mV
170 265 350 mV DataShee
-125
0
125 mV
23.5 27 29.4 PA
3.9 V
7.0 7.5 8.0
6.5 7.0 7.5
400 500 700
4.05 4.36 4.60
3.92 4.17 4.40
100 200 250
V
V
mV
V
V
mV
150 400 mV
0 10 PA
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IR3094PBF
PWM Operation
The IR3094 is a fully integrated 3 phase interleaved PWM control IC which uses voltage mode control with trailing
edge modulation. A high-gain wide-bandwidth voltage type Error Amplifier in the Control IC is used for the voltage
control loop. The PWM block diagram of the IR3094 is shown in Figure 2.
et4U.com
C D AC
R D AC
VR EF
U30
IROSC
CLK1
CLK2 CLK2
CLK3 CLK3
OSC BLOC K
OVP SET
OVP LATCH
S
Q
OVP RESET
QB
R
VOSN S-
VDAC
ERROR AMPLIFIER
PWM COMPARATOR
-
+
RSFF
S
Q
QB
R
RESET DOMINANT
I R OSC / 2
9p 0.6V
FB
CCOMP
RCOMP
EAOU T
I R OSC
RDRP VDRP
VDRP BUFFER
RFB
SC OMP2
0.575V
0% DUTY CYCLE
C LK2
PWM COMPARATOR
R SF F
S
Q
- QB
R
+ RESET DOMINANT
IROSC
Share Adjust Error Amp
+
- 0 TO IROSC*3/4
9p
0.6V
CSC2
RSC2
RSFF
DataSheet4U.comCLK3 S
PWM COMPARATOR
Q
EAOUT -
QB
R
+ RESET DOMINANT
IROSC
SC OMP3
CSC3
RSC3
Share Adjust Error Amp
+
- 0 TO IROSC*3/4
9p
0.6V
VDAC
VDAC
VDAC
X23.5 -
+
X23.5 -
+
X23.5 -
+
GATEH 1
VI N
GATEL1
12
RCS1 CCS1
GATEH 2
GATEL2
VI N
12
RCS2 CCS2
GATEH 3
GATEL3
VI N
12
RCS3 CCS3
C SI N M3
C SI N P3
C SI N M2
C SI N P2
C SI N M1
C SI N P1
VOUT SENSE+
VOUT+
COUT
VOUT-
VOUT SENSE-
DataShee
Figure 2 – PWM Block Diagram
Refer to Figure 3. Upon receiving a clock pulse, the RSFF is set, the internal PWM ramp voltage begins to
increase, the low side driver is turned off, and the high side driver is then turned on. For phase 1, an internal 9pf
capacitor is charged by a current source that proportional to the switching frequency resulting in a ramp rate of
50mV per percent duty cycle. For example, if the steady-state operating switch node duty cycle is 10%, then the
internal ramp amplitude is typically 500mV from the starting point (or floor) to the crossing of the EAOUT control
voltage. When the PWM ramp voltage exceeds the Error Amplifier’s output voltage, the RSFF is reset. This turns
off the high side driver, turns on the low side driver, and discharges the PWM ramp to 0.6V until the next clock
pulse.
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Páginas | Total 29 Páginas | |
PDF Descargar | [ Datasheet IR3094PBF.PDF ] |
Número de pieza | Descripción | Fabricantes |
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