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PDF ST93C66 Data sheet ( Hoja de datos )
| Número de pieza | ST93C66 | |
| Descripción | (ST93C66 / ST93C67) 4K 256 x 16 or 512 x 8 SERIAL MICROWIRE EEPROM | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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ST93C66
ST93C67
4K (256 x 16 or 512 x 8) SERIAL MICROWIRE EEPROM
NOT FOR NEW DESIGN
1 MILLION ERASE/WRITE CYCLES, with
40 YEARS DATA RETENTION
DUAL ORGANIZATION: 256 x 16 or 512 x 8
BYTE/WORD and ENTIRE MEMORY
PROGRAMMING INSTRUCTIONS
SELF-TIMED PROGRAMMING CYCLE with
AUTO-ERASE
READY/BUSY SIGNAL DURING
PROGRAMMING
SINGLE SUPPLY VOLTAGE:
– 4.5V to 5.5V for ST93C66 version
– 3V to 5.5V for ST93C67 version
SEQUENTIAL READ OPERATION
5ms TYPICAL PROGRAMMING TIME
ST93C66 and ST93C67 are replaced by the
M93C66
8
1
PSDIP8 (B)
0.4mm Frame
8
1
SO8 (CM)
150mil Width
Figure 1. Logic Diagram
DESCRIPTION
This specification covers a range of 4K bit serial
EEPROM products, the ST93C66 specified at 5V
± 10% and the ST93C67 specified at 3V to 5.5V. In
the text, products are referred to as ST93C66.
The ST93C66 is a 4K bit Electrically Erasable
Programmable Memory (EEPROM) fabricated with
SGS-THOMSON’s High EnduranceSingle Polysili-
con CMOS technology. The memory is accessed
through a serial input (D) and output (Q). The 4K
bit memory is divided into either 512 x 8 bit bytes
or 256 x 16 bit words. The organization may be
selected by a signal applied on the ORG input.
Table 1. Signal Names
S Chip Select Input
D Serial Data Input
Q Serial Data Output
C Serial Clock
ORG
Organisation Select
VCC Supply Voltage
VSS Ground
D
C
S
ORG
VCC
ST93C66
ST93C67
VSS
Q
AI01252B
July 1997
This is information on a product still in production bu t not recommended for new de signs.
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Figure 5. Synchronous Timing, Read or Write
C
S
tDVCH
tCHDX
D An
A0
Hi-Z
Q
tCHQL
ADDRESS INPUT
ST93C66, ST93C67
tCHQV
Q15/Q7
tCLSL
tSLSH
tSLQZ
Q0
DATA OUTPUT
AI00820C
C
S
tDVCH
D An
Hi-Z
Q
tCHDX
A0/D0
ADDRESS/DATA INPUT
tSLCH
tCLSL
tSLSH
tSHQV tSLQZ
BUSY
READY
tW
WRITE CYCLE
AI01429
MEMORY ORGANIZATION
The ST93C66 is organized as 512 bytes x 8 bits or
256 words x 16 bits. If the ORG input is left uncon-
nected (or connected to VCC) the x16 organization
is selected, when ORG is connected to Ground
(VSS) the x8 organization is selected. When the
ST93C66 is in standby mode, the ORG input
should be unconnected or set to either VSS or VCC
in order to achieve the minimum power consump-
tion. Any voltage between VSS and VCC applied to
ORG may increase the standby current value.
POWER-ON DATA PROTECTION
In order to prevent data corruption and inadvertent
write operations during power up, a Power On
Reset (POR) circuit resets all internal programming
circuitry and sets the device in the Write Disable
mode. When VCC reaches its functional value, the
device is properly reset (in the Write Disable mode)
and is ready to decode and execute an incoming
instruction. A stable VCC must be applied, before
applying any logic signal.
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ST93C66, ST93C67
Symb
A
A1
A2
B
B1
C
D
E
E1
e1
eA
eB
L
N
CP
PSDIP8
PSDIP8 - 8 pin Plastic Skinny DIP, 0.4mm lead frame
Typ
7.62
2.54
mm
Min
0.70
3.10
0.38
1.15
0.38
9.20
–
6.30
–
8.40
3.00
8
inches
Max Typ Min
4.80
– 0.028
3.60 0.122
0.58 0.015
1.65 0.045
0.52 0.015
9.90 0.362
– 0.300 –
7.10 0.248
– 0.100 –
– 0.331
9.20
3.80 0.118
8
0.10
Max
0.189
–
0.142
0.023
0.065
0.020
0.390
–
0.280
–
–
0.362
0.150
0.004
A2 A
A1 L
B e1
B1
D
N
E1 E
1
C
eA
eB
PSDIP-a
Drawing is not to scale.
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| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet ST93C66.PDF ] | |
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| ST93C67 | (ST93C66 / ST93C67) 4K 256 x 16 or 512 x 8 SERIAL MICROWIRE EEPROM | ST Microelectronics |
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