|
|
PDF DP8390D Data sheet ( Hoja de datos )
| Número de pieza | DP8390D | |
| Descripción | NIC Network Interface Controller | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de DP8390D (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
www.DataSheet4U.com
July 1995
DP8390D NS32490D NIC Network Interface Controller
General Description
The DP8390D NS32490D Network Interface Controller
(NIC) is a microCMOS VLSI device designed to ease inter-
facing with CSMA CD type local area networks including
Ethernet Thin Ethernet (Cheapernet) and StarLAN The
NIC implements all Media Access Control (MAC) layer func-
tions for transmission and reception of packets in accord-
ance with the IEEE 802 3 Standard Unique dual DMA chan-
nels and an internal FIFO provide a simple yet efficient
packet management design To minimize system parts
count and cost all bus arbitration and memory support logic
are integrated into the NIC
The NIC is the heart of a three chip set that implements the
complete IEEE 802 3 protocol and node electronics as
shown below The others include the DP8391 Serial Net-
work Interface (SNI) and the DP8392 Coaxial Transceiver
Interface (CTI)
Features
Y Compatible with IEEE 802 3 Ethernet II Thin Ethernet
StarLAN
Y Interfaces with 8- 16- and 32-bit microprocessor
systems
Y Implements simple versatile buffer management
Y Requires single 5V supply
Y Utilizes low power microCMOS process
Y Includes
Two 16-bit DMA channels
16-byte internal FIFO with programmable threshold
Network statistics storage
Y Supports physical multicast and broadcast address
filtering
Y Provides 3 levels of loopback
Y Utilizes independent system and network clocks
Table of Contents
1 0 SYSTEM DIAGRAM
2 0 BLOCK DIAGRAM
3 0 FUNCTIONAL DESCRIPTION
4 0 TRANSMIT RECEIVE PACKET ENCAPSULATION
DECAPSULATION
5 0 PIN DESCRIPTIONS
6 0 DIRECT MEMORY ACCESS CONTROL (DMA)
7 0 PACKET RECEPTION
8 0 PACKET TRANSMISSION
9 0 REMOTE DMA
10 0 INTERNAL REGISTERS
11 0 INITIALIZATION PROCEDURES
12 0 LOOPBACK DIAGNOSTICS
13 0 BUS ARBITRATION AND TIMING
14 0 PRELIMINARY ELECTRICAL CHARACTERISTICS
15 0 SWITCHING CHARACTERISTICS
16 0 PHYSICAL DIMENSIONS
1 0 System Diagram
IEEE 802 3 Compatible Ethernet Thin Ethernet Local Area Network Chip Set
TRI-STATE is a registered trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL F 8582
TL F 8582 – 1
RRD-B30M105 Printed in U S A
DataSheet4 U .com
www.DataSheet4U.com
www.DataSheet4U.com
1 page  
www.DataSheet4U.com
5 0 Pin Descriptions (Continued)
BUS INTERFACE PINS (Continued)
Symbol
CS
MWR
MRD
SWR
SRD
ACK
RA0 – RA3
PRD
WACK
INT
RESET
BREQ
BACK
PRQ ADS1
READY
DIP Pin No
19
20
21
22
23
24
45 – 48
44
43
42
41
31
30
29
28
Function
I
OZ
OZ
I
I
O
I
O
I
O
I
O
I
OZ
I
Description
CHIP SELECT Chip Select places controller in slave mode for mP access to
internal registers Must be valid through data portion of bus cycle RA0 – RA3 are
used to select the internal register SWR and SRD select direction of data
transfer
MASTER WRITE STROBE Strobe for DMA transfers active low during write
cycles (t2 t3 tw) to buffer memory Rising edge coincides with the presence of
valid output data TRI-STATE until BACK asserted
MASTER READ STROBE Strobe for DMA transfers active during read cycles
(t2 t3 tw) to buffer memory Input data must be valid on rising edge of MRD
TRI-STATE until BACK asserted
SLAVE WRITE STROBE Strobe from CPU to write an internal register selected
by RA0 – RA3
SLAVE READ STROBE Strobe from CPU to read an internal register selected
by RA0 – RA3
ACKNOWLEDGE Active low when NIC grants access to CPU Used to insert
WAIT states to CPU until NIC is synchronized for a register read or write
operation
REGISTER ADDRESS These four pins are used to select a register to be read
or written The state of these inputs is ignored when the NIC is not in slave mode
(CS high)
PORT READ Enables data from external latch onto local bus during a memory
write cycle to local memory (remote write operation) This allows asynchronous
transfer of data from the system memory to local memory
WRITE ACKNOWLEDGE Issued from system to NIC to indicate that data has
been written to the external latch The NIC will begin a write cycle to place the
data in local memory
INTERRUPT Indicates that the NIC requires CPU attention after reception
transmission or completion of DMA transfers The interrupt is cleared by writing
to the ISR All interrupts are maskable
RESET Reset is active low and places the NIC in a reset mode immediately no
packets are transmitted or received by the NIC until STA bit is set Affects
Command Register Interrupt Mask Register Data Configuration Register and
Transmit Configuration Register The NIC will execute reset within 10 BUSK
cycles
BUS REQUEST Bus Request is an active high signal used to request the bus for
DMA transfers This signal is automatically generated when the FIFO needs
servicing
BUS ACKNOWLEDGE Bus Acknowledge is an active high signal indicating that
the CPU has granted the bus to the NIC If immediate bus access is desired
BREQ should be tied to BACK Tying BACK to VCC will result in a deadlock
PORT REQUEST ADDRESS STROBE 1
32-BIT MODE If LAS is set in the Data Configuration Register this line is
programmed as ADS1 It is used to strobe addresses A16 – A31 into external
latches (A16 – A31 are the fixed addresses stored in RSAR0 RSAR1 ) ADS1
will remain at TRI-STATE until BACK is received
16-BIT MODE If LAS is not set in the Data Configuration Register this line is
programmed as PRQ and is used for Remote DMA Transfers In this mode
PRQ will be a standard logic output
NOTE This line will power up as TRI-STATE until the Data Configuration
Register is programmed
READY This pin is set high to insert wait states during a DMA transfer The NIC
will sample this signal at t3 during DMA transfers
5
DataSheet4 U .com
www.DataSheet4U.com
www.DataSheet4U.com
5 Page 
www.DataSheet4U.com
7 0 Packet Reception (Continued)
3 After a packet is DMAed from the Receive Buffer Ring
the Next Page Pointer (second byte in NIC buffer header)
is used to update BNDRY and next pkt
next pkt e Next Page Pointer
BNDRY e Next Page Pointer b 1
If BNDRY k PSTART then BNDRY e PSTOP b 1
Note the size of the Receive Buffer Ring is reduced by one
256-byte buffer this will not however impede the operation
of the NIC
In StarLAN applications using bus clock frequencies greater
than 4 MHz the NIC does not update the buffer header
information properly because of the disparity between the
network and bus clock speeds The lower byte count is cop-
ied twice into the third and fourth locations of the buffer
header and the upper byte count is not written The upper
byte count however can be calculated from the current
next page pointer (second byte in the buffer header) and the
previous next page pointer (stored in memory by the CPU)
The following routine calculates the upper byte count and
allows StarLAN applications to be insensitive to bus clock
speeds Next pkt is defined similarly as above
1st Received Packet Removed By Remote DMA
TL F 8582 – 57
upper byte count e next page pointer b next pkt b 1
if (upper byte count) k 0 then
upper byte count e (PSTOP b next pkt) a
(next page pointer b PSTART) b 1
if (lower byte count) l 0 fch then
upper byte count e upper byte count a 1
STORAGE FORMAT FOR RECEIVED PACKETS
The following diagrams describe the format for how re-
ceived packets are placed into memory by the local DMA
channel These modes are selected in the Data Configura-
tion Register
Storage Format
AD15
AD8 AD7
AD0
Next Packet
Pointer
Receive
Status
Receive
Byte Count 1
Receive
Byte Count 0
Byte 2
Byte 1
BOS e 0 WTS e 1 in Data Configuration Register
This format used with Series 32000 808X type processors
AD15
AD8 AD7
AD0
Next Packet
Pointer
Receive
Status
Receive
Byte Count 0
Receive
Byte Count 1
Byte 1
Byte 2
BOS e 1 WTS e 1 in Data Configuration Register
This format used with 68000 type processors
Note The Receive Byte Count ordering remains the same for BOSe0 or 1
AD7 AD0
Receive Status
Next Packet
Pointer
Receive Byte
Count 0
Receive Byte
Count 1
Byte 0
Byte 1
BOS e 0 WTS e 0 in Data Configuration Register
This format used with general 8-bit CPUs
8 0 Packet Transmission
The Local DMA is also used during transmission of a pack-
et Three registers control the DMA transfer during trans-
mission a Transmit Page Start Address Register (TPSR)
and the Transmit Byte Count Registers (TBCR0 1) When
the NIC receives a command to transmit the packet pointed
to by these registers buffer memory data will be moved into
the FIFO as required during transmission The NIC will gen-
erate and append the preamble synch and CRC fields
TRANSMIT PACKET ASSEMBLY
The NIC requires a contiguous assembled packet with the
format shown The transmit byte count includes the Destina-
tion Address Source Address Length Field and Data It
does not include preamble and CRC When transmitting
data smaller than 46 bytes the packet must be padded to a
minimum size of 64 bytes The programmer is responsible
for adding and stripping pad bytes
General Transmit Packet Format
TL F 8582 – 58
11
DataSheet4 U .com
www.DataSheet4U.com
www.DataSheet4U.com
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet DP8390D.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| DP83901A | Serial Network Interface Controller | National Semiconductor |
| DP83901A | DP83901A SNIC Serial Network Interface Controller (Rev. A) |  Texas Instruments |
| DP83902A | ST-NICTM Serial Network Interface Controller for Twisted Pair | National Semiconductor |
| DP83902A | DP83902A ST-NIC Serial Network Interface Controller for Twisted Pair (Rev. A) | Texas Instruments |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |