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PDF DP83905 Data sheet ( Hoja de datos )
| Número de pieza | DP83905 | |
| Descripción | AT Local Area Network Twisted-Pair Interface Controller | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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PRELIMINARY
November 1995
DP83905 AT LANTICTM
AT Local Area Network Twisted-Pair
Interface Controller
General Description
The AT LANTIC AT Local Area Network Twisted-pair Inter-
face Controller is a CMOS VLSI device designed for easy
implementation of CSMA CD local area networks
Unique to the AT LANTIC is the integration of the entire bus
interface for PC-AT ISA (Industry Standard Architecture)
bus based systems Hardware and software selectable op-
tions allow the AT LANTIC’s bus interface to be configured
software compatible to either an NE2000 or Ethercard
PLUS16TM All bus drivers and control logic are integrated
to reduce board cost and area
Supported network interfaces include 10BASE5 or
10BASE2 Ethernet via an external transciever connected to
its AUI port and Twisted-pair Ethernet (10BASE-T) using
the on-board transceiver The AT LANTIC provides the
Ethernet Media Access Control (MAC) Encode-Decode
(ENDEC) with an AUI interface and 10BASE-T transceiver
functions in accordance with the IEEE 802 3 standards
The AT LANTIC’s integrated 10BASE-T transceiver fully
complies with the IEEE standard This functional block incor-
porates the receiver transmitter collision heartbeat Ioop-
back jabber and link integrity blocks as defined in the stan-
dard The transceiver when combined with equalization re-
sistors transmit receive filters and pulse transformers pro-
vides a complete physical interface from the AT LANTIC
Controller’s ENDEC module and the twisted pair medium
(Continued)
Features
Y Controller and integrated bus interface solution for IEEE
802 3 10BASE5 10BASE2 and 10BASE-T
Y Software compatible with Novell ’s NE2000 Plus indus-
try standard Ethernet Adapters
Y Selectable buffer memory size
Y No external bus logic or drivers
Y Integrated controller ENDEC and transceiver
Y Full IEEE 802 3 AUI interface
Y Single 5V supply
10BASE-T TRANSCEIVER MODULE
Y Integrates transceiver functionality
Transmitter and receiver functions
Collision detect heartbeat and jabber
Selectable link integrity test or link disable
Polarity Detection Correction
ENDEC MODULE
Y 10 Mbit s Manchester encoding decoding
Y Squelch on receive and collision pairs
MAC CONTROLLER MODULE
Y Software compatible with DP8390 DP83901 DP83902
Y Efficient buffer management implementation
1 0 System Diagram
TRI-STATE is a registered trademark of National Semiconductor Corporation
AT LANTICTM is a trademark of National Semiconductor Corporation
PC-AT is a registered trademark of International Business Machines Corp
Novell is a registered trademark of Novell Inc
EtherCard PLUSTM and EtherCard PLUS 16TM are trademarks of Standard Microsystems Corp
C1995 National Semiconductor Corporation TL F 11498
TL F 11498 – 1
RRD-B30M115 Printed in U S A
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2 0 Pin Description (Continued)
Pin No
Pin Name
Type
Description
ISA BUS INTERFACE PINS (Continued)
123 CHRDY
O CHANNEL READY This signal is used to insert wait states into system accesses
OCH
122 AEN
I DMA ACTIVE This signal indicates that the system’s DMA controller has control
TTL of the bus
89–92 INT0–3
O
3SH
INTERRUPT REQUEST The operation of these 4 outputs is determined by the
Configuration registers They can either be used to directly drive the interrupt lines
or used as a 3-bit code with a strobe to generate up to 8 interrupts
61 DWID
I
MOS
DATA WIDTH This input specifies whether the AT LANTIC Controller is
interfacing to an 8- or 16-bit ISA bus When high it is in 16-bit mode It has an
internal pull-down resistor
93 lSACLK
I ISA CLOCK Clock from ISA bus This signal is only required if CHRDY timing has
TTL to be altered by changing the CHRDY bit of Configuration Register B
NETWORK INTERFACE PINS
156–153 TXOda TXOb
TXOa TXOdb
O TWISTED PAIR TRANSMIT OUTPUTS These high drive CMOS level outputs
TPI are resistively combined external to the chip to produce a differential output signal
with equalization to compensate for Intersymbol Interference (lSI) on the twisted
pair medium
150 151 RXIa RXIb
I TWISTED PAIR RECEIVE INPUTS These inputs feed a differential amplifier
TPI which passes valid data to the ENDEC module
141 TXb
142 TXa
O AUI TRANSMIT OUTPUT Differential driver which sends the encoded data to the
AUI transceiver The outputs are source followers which require 270X pull-down
resistors
145 RXb
146 RXa
I AUI RECEIVE INPUT Differential receive input pair from the transceiver
AUI
147 CDb
148 CDa
I AUI COLLISION INPUT Differential collision pair input from the transceiver
AUI
5 TXLED
O
LED
TRANSMIT An open-drain active Iow output It is asserted for approximately
50 ms whenever the AT LANTIC Controller transmits data in either AUI or TPI
modes
4 RXLED
O RECEIVE An open-drain active low output It is asserted for approximately 50 ms
LED whenever receive data is detected in either AUI or TPI mode
3 COLED
O
LED
COLLISION An open-drain active Iow output It is asserted for approximately 50
ms whenever the AT LANTIC Controller detects a collision in either AUI or TPI
modes
1 GDLNK
O GOOD LINK An open-drain active low output This pin operates as an output to
LED display link integrity status if this function has not been disabled by the GDLNK bit
in Configuration Register B
This output is off if the AT LANTIC Controller is in AUI mode or if link testing is
enabled and the link integrity is bad (i e the twisted pair link has been broken)
This output is on if the AT LANTIC Controller is in Twisted Pair Interface (TPI)
mode link integrity checking is enabled and the link integrity is good (i e the
twisted pair link has not been broken) or if the link testing is disabled
2 POLED
O
LED
POLARITY An open-drain active low output This signal is normally inactive
When the TPI module detects seven consecutive link pulses or three consecutive
received packets with reversed polarity POLED is asserted
Driver Types are I e Input O e Output I O e Bi-directional Output OCH e Open Collector 3SH e TRI-STATE Output TTL e TTL Compatible AUI e
Attachment Unit Interface TPI e Twisted Pair Interface LED e LED Drive MOS e CMOS Level Compatible XTAL e Crystal
5
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4 0 Functional Description (Continued)
16-BIT I O PORT COMPATIBLE MODE I O ADDRESS
MAPPING
This mode is compatible with Novell’s NE2000 The base
I O address of the AT LANTIC Controller is configured by
Configuration Register A (either upon power up or by soft-
ware writing to this register) At that address the following
structure appears
Base a 00H
DP8390
Core
Registers
Base a 0FH
Base a 10H
Base a 17H
Base a 18H
Base a 1FH
Data Transfer Port
Reset Port
FIGURE 5 I O Port Mode Register I O Map
The registers within this area are 8 bits wide but the data
transfer port is 16 bits wide The AT LANTIC Controller’s
registers can be programmed to control the passing of data
between its internal memory and the data transfer port By
accessing the data transfer port (using I O instructions) the
user can transfer data to or from the AT LANTIC Control-
ler’s internal memory The AT LANTIC Controller’s internal
memory map is as shown in Figure 6
AT LANTIC Controller actually has a 64k address range but
only does partial decoding on these devices The PROM
data is mirrored at all decodes up to 4000H and the entire
map is repeated at 8000H To access either the PROM or
the RAM the user must initiate a Remote DMA transfer be-
tween the I O port and memory
On a remote read the AT LANTIC Controller moves data
from its internal memory map to the I O port and the host
system reads it by using an ‘‘INW’’ or ‘‘INSW’’ instruction
from the I O address of the data transfer port If the system
attempts to read the port before AT LANTIC Controller has
written the next word of data to it AT LANTIC Controller will
insert wait states into the system cycle using the CHRDY
0000H D15
001FH
D0
PROM
4000H
7FFFH
8000H
C000H
FFFFH
Aliased PROM
8k x 16
Buffer RAM
Aliased PROM
Aliased
Buffer RAM
(a)
D15 D0
1EH 00
57H
1CH 00
57H
00 RESERVED
0AH 00 E’net Address 5
08H 00 E’net Address 4
06H 00 E’net Address 3
04H 00 E’net Address 2
02H 00 E’net Address 1
00H 00 E’net Address 0
(b)
FIGURE 6 a) NIC Core’s Memory Map
b) 16-Bit Prom Map
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet DP83905.PDF ] | |
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