|
|
PDF DP83902A Data sheet ( Hoja de datos )
| Número de pieza | DP83902A | |
| Descripción | ST-NICTM Serial Network Interface Controller for Twisted Pair | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de DP83902A (archivo pdf) en la parte inferior de esta página. Total 70 Páginas | ||
|
No Preview Available !
www.DataSheet4U.com
PRELIMINARY
November 1995
DP83902A ST-NICTM
Serial Network Interface Controller for Twisted Pair
General Description
The DP83902A Serial Network Interface Controller for
Twisted Pair (ST-NIC) is a microCMOS VLSI device de-
signed for easy implementation of CSMA CD local area net-
works These include Ethernet (10BASE5) Thin Ethernet
(10BASE2) and Twisted-pair Ethernet (10BASE-T) The
overall ST-NIC solution provides the Media Access Control
(MAC) and Encode-Decode (ENDEC) with an AUI interface
and 10BASE-T transceiver functions in accordance with the
IEEE 802 3 standards
The DP83902A’s 10BASE-T transceiver fully complies with
the IEEE standard This functional block incorporates the
receiver transmitter collision heartbeat loopback jabber
and link integrity blocks as defined in the standard The
transceiver when combined with equalization resistors
transmit receive filters and pulse transformers provides a
complete physical interface from the DP83902A’s ENDEC
module and the twisted pair medium
The integrated ENDEC module allows Manchester encod-
ing and decoding via a differential transceiver and phase
lock loop decoder at 10 Mbit sec Also included are colli-
sion detect translator and diagnostic loopback capability
The ENDEC module interfaces directly to the transceiver
module and also provides a fully IEEE compliant AUI (At-
tachment Unit Interface) for connection to other media
transceivers
(Continued)
Features
Y Single chip solution for IEEE 802 3 10BASE-T
Y Integrated controller ENDEC and transceiver
Y Full AUI interface
Y No external precision components required
Y 3 levels of loopback supported
Transceiver Module
Y Integrates transceiver electronics including
Transmitter and receiver
Collision detect heartbeat and jabber timer
Link integrity test
Y Link disable and polarity detection correction
Y Integrated smart receive squelch
Y Reduced squelch level for extended distance cable op-
eration (100-pin QFP version)
ENDEC Module
Y 10 Mb s Manchester encoding decoding plus clock re-
covery
Y Transmitter half or full step mode
Y Squelch on receive and collision pairs
Y Lock time 5 bits typical
Y Decodes Manchester data with up to g18 ns jitter
MAC Controller Module
Y 100% DP8390 software hardware compatible
Y Dual 16-bit DMA channels
Y 16-byte internal FIFO
Y Efficient buffer management implementation
Y Independent system and network clocks
Y Supports physical multicast and broadcast address fil-
tering
Y Network statistics storage
1 0 System Diagram
Station or DTE
TRI-STATE is a registered trademark of National Semiconductor Corporation
ST-NICTM is a trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL F 11157
TL F 11157 – 1
RRD-B30M115 Printed in U S A
DataSheet4 U .com
www.DataSheet4U.com
www.DataSheet4U.com
1 page  
www.DataSheet4U.com
2 0 Pin Description (Continued)
PQFP
Pin No
PLCC AVJG
Pin No Pin No
Pin
Name
BUS INTERFACE PINS (Continued)
4–8
10 – 12
14 15 17
18 22 23
25 26
12 – 23
28 – 31
2–4 6
7 9–15
20 – 23
AD0 –
AD15
27 32 25 ADS0
28 33 26 CS
29 34 27 MWR
30 35 28 MRD
31 36 29 SWR
32 37 30 SRD
33 38 31 ACK
36 40 34 BSCK
37 41 35 RACK
39 42 36 PWR
41 43 37 READY
42 44 39 PRQ
ADS1
IO
IOZ
IOZ
I
OZ
OZ
I
I
O
I
I
O
I
OZ
Description
MULTIPLEXED ADDRESS DATA BUS
Register Access with DMA inactive CS low and ACK returned from
DP83902A pins AD0–AD7 are used to read and write register data AD8–
AD15 float during I O transfers SRD SWR pins are used to select
direction of transfer
Bus Master with BACK input asserted
During t1 of memory cycle AD0 – AD15 contain address
During t2 t3 t4 AD0 – AD15 contain data (word transfer mode)
During t2 t3 t4 AD0–AD7 contain data AD8–AD15 contain address (byte
transfer mode)
Direction of transfer is indicated by DP83902A on MWR MRD lines
ADDRESS STROBE 0
Input with DMA inactive and CS low latches RA0–RA3 inputs on falling
edge If high data present on RA0–RA3 will flow through latch
Output When Bus Master latches address bits (AD0–AD15) to external
memory during DMA transfers
CHIP SELECT Chip Select places controller in slave mode for mP access to
internal registers Must be valid through data portion of bus cycle RA0 – RA3
are used to select the internal register SWR and SRD select direction of
data transfer
MASTER WRITE STROBE (Strobe for DMA transfers)
Active low during write cycles (t2 t3 tw) to buffer memory Rising edge
coincides with the presence of valid output data TRI-STATE until BACK
asserted
MASTER READ STROBE (Strobe for DMA transfers)
Active during read cycles (t2 t3 tw) to buffer memory Input data must be
valid on rising edge of MRD TRI-STATE until BACK asserted
SLAVE WRITE STROBE Strobe from CPU to write an internal register
selected by RA0 – RA3 Data is latched into the DP83902A on the rising
edge of this input
SLAVE READ STROBE Strobe from CPU to read an internal register
selected by RA0 – RA3 The register data is output when SRD goes low
ACKNOWLEDGE Active low when DP83902A grants access to CPU Used
to insert WAIT states to CPU until DP83902A is synchronized for a register
read or write operation
BUS CLOCK This clock is used to establish the period of the DMA memory
cycle Four clock cycles (t1 t2 t3 t4) are used per DMA cycle DMA
transfers can be extended by one BSCK increment using the READY input
READ ACKNOWLEDGE Indicates that the system DMA or host CPU has
read the data placed in the external latch by the DP83902A The DP83902A
will begin a read cycle to update the latch
PORT WRITE Strobe used to latch data from the DP83902A into external
latch for transfer to host memory during Remote Read transfers The rising
edge of PWR coincides with the presence of valid data on the local bus
READY This pin is set high to insert wait states during a DMA transfer The
DP83902A will sample this signal at t3 during DMA transfers
PORT REQUEST ADDRESS STROBE 1
32-BIT MODE If LAS is set in the Data Configuration Register this line is
programmed as ADS1 It is used to strobe addresses A16 – A31 into
external latches (A16 – A31 are the fixed addresses stored in RSAR0
RSAR1) ADS1 will remain at TRI-STATE until BACK is received
16-BIT MODE If LAS is not set in the Data Configuration Register this
line is programmed as PRQ and is used for Remote DMA Transfers The
DP83902A initiates a single remote DMA read or write operation by
asserting this pin In this mode PRQ will be a standard logic output
Note This line will power up as TRI-STATE until the Data Configuration Register is programmed
5
DataSheet4 U .com
www.DataSheet4U.com
www.DataSheet4U.com
5 Page 
www.DataSheet4U.com
4 0 Functional Description (Continued)
In order to prevent distortion on the transmitted frequency
the total capacitance seen by the crystal should equal the
total load capacitance On a standard parallel set-up as
shown in the diagram below the 2 load caps C1 and C2
should equal 2C1 the spec load cap (due to the capacitors
acting in series) less any stray capacitances
Thus the trim capacitors required can be calculated as fol-
lows
C1e2XC1b(Cb1aCd1) Where Cb1eBoard cap on X1
and Cd1eX1 dev cap
C2e2XC1b(Cb2aCd2) Where Cb2eBoard cap on X2
and Cd2eX2 dev cap
The value of STNIC pins X1 and X2 is in the region of 5 pF
TL F 11157 – 52
NIC (Media Access Control) MODULE
RECEIVE DESERIALIZER
The Receive Deserializer is activated when the input signal
Carrier Sense is asserted to allow incoming bits to be shift-
ed into the shift register by the receive clock The serial
receive data is also routed to the CRC generator checker
The Receive Deserializer includes a synch detector which
detects the SFD (Start of Frame Delimiter) to establish
where byte boundaries within the serial bit stream are locat-
ed After every eight receive clocks the byte wide data is
transferred to the 16-byte FIFO and the Receive Byte Count
is incremented The first six bytes after the SFD are
checked for valid comparison by the Address Recognition
Logic If the Address Recognition Logic does not recognize
the packet the FIFO is cleared
CRC GENERATOR CHECKER
During transmission the CRC logic generates a local CRC
field for the transmitted bit sequence The CRC encodes all
fields after the SFD The CRC is shifted out MSB first follow-
ing the last transmit byte During reception the CRC logic
generates a CRC field from the incoming packet This local
CRC is serially compared to the incoming CRC appended to
the end of the packet by the transmitting node If the local
and received CRC match a specific pattern will be generat-
ed and decoded to indicate no data errors Transmission
errors result in different pattern and are detected resulting
in rejection of a packet (if so programmed)
TRANSMIT SERIALIZER
The Transmit Serializer reads parallel data from the FIFO
and serializes it for transmission The serializer is clocked by
the transmit clock generated internally The serial data is
also shifted into the CRC generator checker At the begin-
ning of each transmission the Preamble and Synch Gener-
ator append 62 bits of 1 0 preamble and a 1 1 synch pat-
tern After the last data byte of the packet has been serial-
ized the 32-bit FCS field is shifted directly out of the CRC
generator In the event of a collision the Preamble and
Synch generators are used to generate a 32-bit JAM pattern
of all 1’s
ADDRESS RECOGNITION LOGIC
The address recognition logic compares the Destination Ad-
dress Field (first 6 bytes of the received packet) to the Phys-
ical address registers stored in the Address Register Array
If any one of the six bytes does not match the pre-pro-
grammed physical address the Protocol Control Logic re-
jects the packet All multicast destination addresses are fil-
tered using a hashing technique (See register description )
If the multicast address indexes a bit that has been set in
the filter bit array of the Multicast Address Register Array
the packet is accepted otherwise it is rejected by the Proto-
col Control Logic Each destination address is also checked
for all 1’s which is the reserved broadcast address
FIFO AND BUS OPERATIONS
Overview
To accommodate the different rates at which data comes
from (or goes to) the network and goes to (or comes from)
the system memory the ST-NIC contains a 16-byte FIFO for
buffering data between the media The FIFO threshold is
programmable When the FIFO has filled to its programmed
threshold the local DMA channel transfers these bytes (or
words) into local memory It is crucial that the local DMA is
given access to the bus within a minimum bus latency time
otherwise a FIFO underrun (or overrun) occurs
FIFO underruns or overruns are caused by two conditions
(1) the bus latency is so long that the FIFO has filled (or
emptied) from the network before the local DMA has serv-
iced the FIFO and (2) the bus latency has slowed the
throughput of the local DMA to a point where it is slower
than the network data rate (10 Mbit sec) This second con-
dition is also dependent upon DMA clock and word width
(byte wide or word wide) The worst case condition ultimate-
ly limits the overall bus latency which the ST-NIC can toler-
ate
Beginning of Receive
At the beginning of reception the ST-NIC stores the entire
Address field of each incoming packet in the FIFO to deter-
mine whether the address matches the ST-NIC’s Physical
Address Registers or maps to one of its Multicast Registers
This causes the FIFO to accumulate 8 bytes Furthermore
there are some synchronization delays in the DMA PLA
Thus the actual time to when BREQ is asserted from the
time the Start of Frame Delimiter (SFD) is detected is
7 8 ms This operation affects the bus latencies at 2- and
4-byte thresholds during the first receive BREQ since the
FIFO must be filled to 8 bytes (or 4 words) before issuing a
BREQ
End of Receive
When the end of a packet is detected by the ENDEC mod-
ule the ST-NIC enters its end of packet processing se-
quence emptying its FIFO and writing the status information
at the beginning of the packet The ST-NIC holds onto the
bus for the entire sequence The longest time BREQ may be
extended occurs when a packet ends just as the ST-NIC
performs its last FIFO burst The ST-NIC in this case per-
forms a programmed burst transfer followed by flushing the
remaining bytes in the FIFO and completes by writing the
header information to memory The following steps occur
during this sequence
1 ST-NIC issues BREQ because the FIFO threshold has
been reached
2 During the burst packet ends resulting in BREQ extend-
ed
11
DataSheet4 U .com
www.DataSheet4U.com
www.DataSheet4U.com
11 Page | ||
| Páginas | Total 70 Páginas | |
| PDF Descargar | [ Datasheet DP83902A.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| DP83902A | ST-NICTM Serial Network Interface Controller for Twisted Pair | National Semiconductor |
| DP83902A | DP83902A ST-NIC Serial Network Interface Controller for Twisted Pair (Rev. A) |  Texas Instruments |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |