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PDF DP83901A Data sheet ( Hoja de datos )

Número de pieza DP83901A
Descripción Serial Network Interface Controller
Fabricantes National Semiconductor 
Logotipo National Semiconductor Logotipo



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November 1995
DP83901A SNIC
Serial Network Interface Controller
General Description
The DP83901A Serial Network Interface Controller (SNIC) is
a microCMOS VLSI device designed for easy implementa-
tion of CSMA CD local area networks These include Ether-
net (10BASE5) Thin Ethernet (10BASE2) and Twisted-pair
Ethernet (10BASE-T) The overall SNIC solution provides
the Media Access Control (MAC) and Encode-Decode
(ENDEC) functions in accordance with the IEEE 802 3 stan-
dard
The integrated ENDEC module allows Manchester encod-
ing and decoding via a differential transceiver and phase
lock loop at 10 Mbit sec Also included is a collision detect
translator and diagnostic loopback capability (Continued)
Features
Y Compatible with IEEE 802 3 10BASE5 10BASE2
10BASE-T
Y Dual 16-byte DMA channels
Y 16-byte internal FIFO
Y Network statistics storage
Y Supports physical multicast and broadcast address
filtering
Y 10 Mbit sec Manchester encoding and decoding plus
clock recovery
Y No external precision components required
Y Efficient buffer management implementation
Y Transmitter can be selected for half or full step mode
Y Integrated squelch on receive and collision pairs
Y 3 levels of loopback supported
Y Utilizes independent system and network clocks
Y Lock Time 5 bits typical
Y Decodes Manchester data with up to g18 ns jitter
1 0 System Diagram
TRI-STATE is a registered trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL F 10469
TL F 10469 – 1
RRD-B30M115 Printed in U S A
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Pin Description (Continued)
Pin No Pin Name I O
Description
POWER SUPPLY PINS
21 48
53 55
VCC
DIGITAL POSITIVE 5V SUPPLY PINS
20 33 49 GND
54 66
DIGITAL NEGATIVE (GROUND) SUPPLY PINS It is suggested that a decoupling capacitor be
connected between the VCC and GND pins
59 VCC
64 GND
AUI RECEIVE 5V SUPPLY Power pin supplies 5V to the AUI receiver
AUI RECEIVE GROUND Ground pin for AUI receiver
45 VCC
44 GND
AUI TRANSMIT 5V SUPPLY Power pin supplies 5V to the AUI transmitter
AUI TRANSMIT GROUND Ground pin for AUI transmitter
58 VCC
VCO 5V SUPPLY Care should be taken to reduce noise on this pin as it supplies 5V to the
ENDEC’s Phase Lock Loop
57 GND
VCO GROUND PIN Care should be taken to reduce noise on this pin as it is the ground to the
ENDEC’s Phase Lock Loop
NO CONNECTION
1 18
35 52
NC
NO CONNECTION Do not connect to these pins
3 0 Block Diagram
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FIGURE 1
TL F 10469 – 3
5
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DP83901A arduino
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7 0 Packet Reception (Continued)
INITIALIZATION OF THE BUFFER RING
Two static registers and two working registers control the
operation of the Buffer Ring These are the Page Start Reg-
ister Page Stop Register (both described previously) the
Current Page Register and the Boundary Pointer Register
The Current Page Register points to the first buffer used to
store a packet and is used to restore the DMA for writing
status to the Buffer Ring or for restoring the DMA address in
the event of a Runt packet a CRC or Frame Alignment
error The Boundary Register points to the first packet in the
Ring not yet read by the host If the local DMA address ever
reaches the Boundary reception is aborted The Boundary
Pointer is also used to initialize the Remote DMA for remov-
ing a packet and is advanced when a packet is removed A
simple analogy to remember the function of these registers
is that the Current Page Register acts as a Write Pointer and
the Boundary Pointer acts as a Read Pointer
Note At initialization the Page Start Register value should be loaded into
both the Current Page Register and the Boundary Pointer Register
Note The Page Start Register must not be initialized to 00H
BEGINNING OF RECEPTION
When the first packet begins arriving the SNIC begins stor-
ing the packet at the location pointed to by the Current Page
Register An offset of 4 bytes is saved in this first buffer to
allow room for storing receive status corresponding to this
packet
Buffer Ring at Initialization
Received Packet Enters the Buffer Pages
TL F 10469 – 8
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TL F 10469 – 9
11
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