|
|
PDF M368L3324CUS Data sheet ( Hoja de datos )
| Número de pieza | M368L3324CUS | |
| Descripción | (M368LxxxxCUx) DDR SDRAM Unbuffered Module | |
| Fabricantes | SAMSUNG | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de M368L3324CUS (archivo pdf) en la parte inferior de esta página. Total 25 Páginas | ||
|
No Preview Available !
www.DataSheet4U.com
256MB, 512MB, 1GB Unbuffered DIMM
DDR SDRAM
DDR SDRAM Unbuffered Module
184pin Unbuffered Module based on 512Mb C-die
with 64/72-bit ECC/Non ECC
66 TSOP-II with Pb-Free
(RoHS compliant)
Revision 1.0
February. 2005
DataSheet4 U .com
Rev. 1.0 February. 2005
www.DataSheet4U.com
www.DataSheet4U.com
1 page  
www.DataSheet4U.com
256MB, 512MB, 1GB Unbuffered DIMM
DDR SDRAM
256MB, 32M x 64 Non ECC Module (M368L3324CUS) (Populated as 1 bank of x16 DDR SDRAM Module)
Functional Block Diagram
DQS1
DM1
DQS0
DM0
CS0
DQ13
DQ14
DQ12
DQ15
DQ9
DQ10
DQ8
DQ11
DQ0
DQ3
DQ4
DQ7
DQ5
DQ2
DQ1
DQ6
LDQS
LDM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDQS
UDM
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
CS
D0
DQS5
DM5
DQS0
DM0
DQ41
DQ42
DQ45
DQ43
DQ44
DQ46
DQ40
DQ47
DQ32
DQ35
DQ36
DQ39
DQ33
DQ38
DQ37
DQ34
LDQS
LDM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDQS
UDM
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
CS
D2
DQS3
DM3
DQS0
DM0
DQ29
DQ26
DQ25
DQ30
DQ28
DQ27
DQ24
DQ31
DQ20
DQ23
DQ16
DQ19
DQ17
DQ22
DQ21
DQ18
LDQS
LDM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDQS
UDM
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
CS
D1
DQS3
DM3
DQS0
DM0
DQ57
DQ62
DQ56
DQ58
DQ61
DQ63
DQ60
DQ59
DQ48
DQ51
DQ52
DQ50
DQ49
DQ55
DQ53
DQ54
LDQS
LDM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDQS
UDM
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
CS
D3
BA0 - BA1
A0 - A12
RAS
CAS
CKE0
WE
VDDSPD
VDD/VDDQ
VREF
VSS
BA0-BA1: DDR SDRAMs D0 - D3
A0-A12: DDR SDRAMs D0 - D3
RAS: DDR SDRAMs D0 - D3
CAS: DDR SDRAMs D0 - D3
CKE: DDR SDRAMs D0 - D3
WE: DDR SDRAMs D0 - D3
Clock Wiring
Clock
Input
DDR SDRAMs
CK0/CK0
CK1/CK1
CK2/CK2
NC
2 DDR SDRAMs
2 DDR SDRAMs
SPD
D0 - D3
D0 - D3
D0 - D3
D0 - D3
SCL
WP
Serial PD
A0 A1 A2
SA0 SA1 SA2
SDA
*Clock Net Wiring
D0/D2
R=120Ω
CK1/2
Card
Edge
*If two DRAMs are loaded,
Cap will replace DRAM
Cap
Cap
Cap
D1/D3
Cap
Notes:
1. DQ-to-I/O wiring is shown as recomended but
may be changed.
2. DQ/DQS/DM/CKE/CS relationships must be
maintained as shown.
3. DQ, DQS, DM/DQS resistors: 22 Ohms + 5%.
4. BAx, Ax, RAS, CAS, WE resistors: 7.5 Ohms
+ 5%
DataSheet4 U .com
Rev. 1.0 February. 2005
www.DataSheet4U.com
www.DataSheet4U.com
5 Page 
www.DataSheet4U.com
256MB, 512MB, 1GB Unbuffered DIMM
DDR SDRAM IDD spec table
DDR SDRAM
M368L3324CUS [ (32M x 16) * 4, 256MB Non ECC Module ]
(VDD=2.7V, T = 10°C)
Symbol
CC(DDR400@CL=3)
B3(DDR333@CL=2.5)
Unit
Notes
IDD0
480
420 mA
IDD1
640
560 mA
IDD2P
20
20 mA
IDD2F
120
120 mA
IDD2Q
100
100 mA
IDD3P
180
120 mA
IDD3N
240
180 mA
IDD4R
760
680 mA
IDD4W
860
740 mA
IDD5
880
820 mA
IDD6
Normal
20
20 mA
Low power
12
12 mA Optional
IDD7A
1,600
1,520
mA
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
DataSheet4 U .com
Rev. 1.0 February. 2005
www.DataSheet4U.com
www.DataSheet4U.com
11 Page | ||
| Páginas | Total 25 Páginas | |
| PDF Descargar | [ Datasheet M368L3324CUS.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| M368L3324CUS | (M368LxxxxCUx) DDR SDRAM Unbuffered Module | SAMSUNG |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |