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PDF M368L2923BUM Data sheet ( Hoja de datos )
| Número de pieza | M368L2923BUM | |
| Descripción | (M368LxxxxBxM) DDR SDRAM Unbuffered Module 184pin Unbuffered Module based on 512Mb B-die | |
| Fabricantes | Samsung semiconductor | |
| Logotipo |  |
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256MB, 512MB, 1GB Unbuffered DIMM
DDR SDRAM
DDR SDRAM Unbuffered Module
184pin Unbuffered Module based on 512Mb B-die
with 64/72-bit Non ECC/ECC
66 TSOP-II
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
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256MB, 512MB, 1GB Unbuffered DIMM
DDR SDRAM
4.0 Pin Configuration (Front side/back side)
Pin Front Pin Front Pin Front Pin Back Pin Back
1
VREF
32
A5
62 VDDQ 93
VSS 124 VSS
2
DQ0
33 DQ24 63
WE
94
DQ4
125
A6
3
VSS
34
VSS
64 DQ41 95
DQ5
126 DQ28
4
DQ1
35 DQ25 65
CAS
96
VDDQ
127
DQ29
5
DQS0 36 DQS3 66
VSS
97
DM0
128 VDDQ
6
DQ2
37
A4
67 DQS5 98
DQ6 129 DM3
7
VDD
38
VDD
68 DQ42 99
DQ7
130
A3
8
DQ3
39
DQ26
69
DQ43
100
VSS
131 DQ30
9
NC
40 DQ27 70
VDD
101
NC
132 VSS
10
NC
41
A2
71
*CS2
102
NC
133 DQ31
11
VSS
42
VSS
72
DQ48
103
NC
134 CB4
12 DQ8 43 A1 73 DQ49 104 VDDQ 135 CB5
13
DQ9
44
CB0
74
VSS
105 DQ12 136 VDDQ
14 DQS1 45
CB1
75
*CK2
106 DQ13 137
CK0
15 VDDQ 46 VDD 76 *CK2 107 DM1 138 CK0
16
CK1
47
DQS8
77
VDDQ
108
VDD
139
VSS
17 CK1 48 A0 78 DQS6 109 DQ14 140 DM8
18 VSS 49 CB2 79 DQ50 110 DQ15 141 A10
19 DQ10 50 VSS 80 DQ51 111 CKE1 142 CB6
20 DQ11 51
CB3
81
VSS
112 VDDQ 143 VDDQ
21 CKE0 52
BA1
82
VDDID
113
*BA2
144
CB7
22 VDDQ
KEY
83 DQ56 114 DQ20
KEY
23
DQ16
53 DQ32 84
DQ57
115
A12
145
VSS
24 DQ17 54 VDDQ 85
VDD 116 VSS 146 DQ36
25 DQS2 55 DQ33 86 DQS7 117 DQ21 147 DQ37
26
VSS
56
DQS4
87
DQ58
118
A11 148 VDD
27
A9
57
DQ34
88
DQ59
119
DM2
149
DM4
28 DQ18 58 VSS 89 VSS 120 VDD 150 DQ38
29 A7 59 BA0 90 NC 121 DQ22 151 DQ39
30 VDDQ 60 DQ35 91
SDA
122
A8
152 VSS
31 DQ19 61 DQ40 92
SCL 123 DQ23 153 DQ44
Note :
1. * : These pins are not used in this module.
2. Pins 44, 45, 47, 49, 51, 134, 135, 140, 142, 144 are used on x72 module ( M381~ ), and are not used on x64 module.
3. Pins 111, 158 are NC for 1row modules & used for 2row modules[ M368(81)L2923B ].
4. Pins 137, 138 are NC for x16 1Row module (M368L3324B).
Pin Back
154 RAS
155 DQ45
156 VDDQ
157 CS0
158 CS1
159 DM5
160 VSS
161 DQ46
162 DQ47
163 *CS3
164 VDDQ
165 DQ52
166 DQ53
167 *A13
168 VDD
169 DM6
170 DQ54
171 DQ55
172 VDDQ
173 NC
174 DQ60
175 DQ61
176 VSS
177 DM7
178 DQ62
179 DQ63
180 VDDQ
181 SA0
182 SA1
183 SA2
184 VDDSPD
5.0 Pin Description
Pin Name
A0 ~ A12
BA0 ~ BA1A
Function
Address input (Multiplexed)
Bank Select Address
DQ0 ~ DQ63
Data input/output
DQS0 ~ DQS8
CK0,CK0 ~ CK2, CK2
CKE0, CKE1(for double banks)
CS0, CS1(for double banks)
RAS
CAS
WE
CB0 ~ CB7(for x72 module)
Data Strobe input/output
Clock input
Clock enable input
Chip select input
Row address strobe
Column address strobe
Write enable
Check bit(Data-in/data-out)
Pin Name
Function
DM0 ~7,8(for ECC) Data - in mask
VDD
Power supply
(2.5V for DDR333, 2.6V for DDR400)
VDDQ
Power Supply for DQS
(2.5V for DDR333, 2.6V for DDR400)
VSS
Ground
VREF
Power supply for reference
VDDSPD Serial EEPROM Power/Supply ( 2.3V to 3.6V )
SDA
Serial data I/O
SCL Serial clock
SA0 ~ 2
Address in EEPROM
VDDID
VDD, VDDQ level detection
NC No connection
Note : VDDID defines relationship of VDD and VDDQ, and the default status of it is open (VDD=VDDQ)
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256MB, 512MB, 1GB Unbuffered DIMM
DDR SDRAM
7.0 Absolute Maximum Ratings
Parameter
Symbol
Value
Voltage on any pin relative to VSS
VIN,VOUT
-0.5 ~ 3.6
Voltage on VDD & VDDQ supply relative to VSS
VDD,VDDQ
-1.0 ~ 3.6
Storage temperature
TSTG
-55 ~ +150
Power dissipation
PD 1.5 * # of component
Short circuit current
IOS 50
Note :
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
Unit
V
V
°C
W
mA
8.0 DC Operating Conditions
Recommended operating conditions(Voltage referenced to VSS=0V, TA=0 to 70°C)
Parameter
Symbol
Min
Max Unit Note
Supply voltage(for device with a nominal VDD of 2.5V for DDR333)
VDD 2.3
2.7 V
Supply voltage(for device with a nominal VDD of 2.6V for DDR400)
VDD 2.5
2.7 V
I/O Supply voltage(for device with a nominal VDD of 2.5V for DDR333)
VDDQ
2.3
2.7 V
I/O Supply voltage(for device with a nominal VDD of 2.6V for DDR400)
VDDQ
2.5
2.7 V
I/O Reference voltage
VREF 0.49*VDDQ 0.51*VDDQ V
1
I/O Termination voltage(system)
Input logic high voltage
VTT
VIH(DC)
VREF-0.04
VREF+0.15
VREF+0.04
VDDQ+0.3
V
V
2
Input logic low voltage
VIL(DC)
-0.3
VREF-0.15
V
Input Voltage Level, CK and CK inputs
VIN(DC)
-0.3
VDDQ+0.3
V
Input Differential Voltage, CK and CK inputs
VID(DC)
0.36
VDDQ+0.6
V
3
V-I Matching: Pullup to Pulldown Current Ratio
VI(Ratio)
0.71
1.4 - 4
Input leakage current
II -2
2 uA
Output leakage current
IOZ -5
5 uA
Output High Current(Normal strengh driver) ;VOUT = VTT + 0.84V
Output High Current(Normal strengh driver) ;VOUT = VTT - 0.84V
Output High Current(Half strengh driver) ;VOUT = VTT + 0.45V
Output High Current(Half strengh driver) ;VOUT = VTT - 0.45V
IOH -16.8
IOL 16.8
IOH -9
IOL 9
mA
mA
mA
mA
Note :
1. VREF is expected to be equal to 0.5*VDDQ of the transmitting device, and to track variations in the dc level of same. Peak-to peak noise on VREF may
not exceed +/-2% of the dc value.
2. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track
variations in the DC level of VREF.
3. VID is the magnitude of the difference between the input level on CK and the input level on CK.
4. The ratio of the pullup current to the pulldown current is specified for the same temperature and voltage, over the entire temperature and voltage range,
for device drain to source voltages from 0.25V to 1.0V. For a given output, it represents the maximum difference between pullup and pulldown drivers
due to process variation. The full variation in the ratio of the maximum to minimum pullup and pulldown current will not exceed 1.7 for device drain to
source voltages from 0.1 to 1.0.
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Rev. 1.1 June 2005
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