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PDF TC74LCX574FT Data sheet ( Hoja de datos )

Número de pieza TC74LCX574FT
Descripción LOW VOLTAGE OCTAL D-TYPE FLIP-FLOP WITH 5V TOLERANT INPUTS AND OUTPUTS
Fabricantes Toshiba Semiconductor 
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TC74LCX574F/FW/FT
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC74LCX574F,TC74LCX574FW,TC74LCX574FT
Low-Voltage Octal D-Type Flip-Flop with 5-V Tolerant Inputs and Outputs
The TC74LCX574F/FW/FT is a high-performance CMOS octal
D-type flip-flop. Designed for use in 3.3-V systems, it achieves
high-speed operation while maintaining the CMOS low power
dissipation.
The device is designed for low-voltage (3.3 V) VCC applications,
but it could be used to interface to 5 V supply environment for
both inputs and outputs.
This 8-bit D-type flip-flop is controlled by a clock input (CK)
and an output enable input (OE). When the OE input is high, the
eight outputs are in a high-impedance state.
All inputs are equipped with protection circuits against static
discharge.
Note: xxxFW (JEDEC SOP) is not available in
Japan.
TC74LCX574F
TC74LCX574FW
Features
· Low-voltage operation: VCC = 2.0 to 3.6 V
· High-speed operation: tpd = 8.5 ns (max) (VCC = 3.0 to 3.6 V)
· Output current: |IOH|/IOL = 24 mA (min) (VCC = 3.0 V)
· Latch-up performance: ±500 mA
· Available in JEDEC SOP, JEITA SOP and TSSOP
www.DataSheet4U.com· Power-down protection provided on all inputs and outputs
TC74LCX574FT
· Pin and function compatible with the 74 series
(74AC/VHC/HC/F/ALS/LS etc.) 574 type
Weight
SOP20-P-300-1.27: 0.22 g (typ.)
SOL20-P-300-1.27: 0.46 g (typ.)
TSSOP20-P-0044-0.65: 0.08 g (typ.)
DataSheet4 U .com
1 2002-01-11
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TC74LCX574FT pdf
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AC Characteristics (Ta = -40 to 85°C)
TC74LCX574F/FW/FT
Characteristics
Maximum clock frequency
Propagation delay time
(CK-Q)
Output enable time
Output disable time
Minimum pulse width
(CK)
Minimum set-up time
Minimum hold time
Output to output skew
Symbol
Test Condition
fmax Figure 1, Figure 2
tpLH
tpHL
tpZL
tpZH
tpLZ
tpHZ
tw (H)
tw (L)
Figure 1, Figure 2
Figure 1, Figure 3
Figure 1, Figure 3
Figure 1, Figure 2
ts Figure 1, Figure 2
th Figure 1, Figure 2
tosLH
tosHL
VCC (V)
2.7
3.3 ± 0.3
2.7
3.3 ± 0.3
2.7
3.3 ± 0.3
2.7
3.3 ± 0.3
2.7
3.3 ± 0.3
2.7
3.3 ± 0.3
2.7
3.3 ± 0.3
2.7
(Note 10)
3.3 ± 0.3
Min
¾
150
¾
1.5
¾
1.5
¾
1.5
3.3
3.3
2.5
2.5
1.5
1.5
¾
¾
Max Unit
¾
MHz
¾
9.5
ns
8.5
9.5
ns
8.5
7.0
ns
6.5
¾
ns
¾
¾
ns
¾
¾
ns
¾
¾
ns
1.0
Note 10: Parameter guaranteed by design.
(tosLH = |tpLHm - tpLHn|, tosHL = |tpHLm - tpHLn|)
Dynamic SwitchingwChwarawcte.rDisticastaSheet4U.com
(Ta = 25°C, input: tr = tf = 2.5 ns, CL = 50 pF, RL = 500 W)
Characteristics
Quiet output maximum
dynamic
Quiet output minimum
dynamic
Symbol
Test Condition
VOL VOLP VIH = 3.3 V, VIL = 0 V
VOL |VOLV| VIH = 3.3 V, VIL = 0 V
Typ.
VCC (V)
3.3 0.8
Unit
V
3.3 0.8
V
Capacitive Characteristics (Ta = 25°C)
Characteristics
Input capacitance
Output capacitance
Power dissipation capacitance
Symbol
CIN
COUT
CPD
fIN = 10 MHz
Test Condition
¾
¾
Typ.
VCC (V)
3.3 7
3.3 8
(Note 11) 3.3
25
Unit
pF
pF
pF
Note 11: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating
current consumption.
Average operating current can be obtained by the equation:
ICC (opr) = CPDVCCfIN + ICC/8 (per bit)
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