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PDF GE28F640W18 Data sheet ( Hoja de datos )

Número de pieza GE28F640W18
Descripción Wireless Flash Memory
Fabricantes Intel Corporation 
Logotipo Intel Corporation Logotipo



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No Preview Available ! GE28F640W18 Hoja de datos, Descripción, Manual

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Intel® Wireless Flash Memory (W18)
28F320W18, 28F640W18, 28F128W18
Datasheet
Product Features
High Performance Read-While-Write/ Architecture
Erase
— Multiple 4-Mbit Partitions
— Burst frequency at 66 MHz
— Dual Operation: RWW or RWE
— 60 ns Initial Access Read Speed
— 8KB parameter blocks
— 11 ns Burst-Mode Read Speed
— 64KB main blocks
— 20 ns Page-Mode Read Speed
— Top or Bottom Parameter Devices
— 4-, 8-, 16-, and Continuous-Word Burst — 16-bit wide data bus
Mode Reads
— Burst and Page Mode Reads in all
Blocks, across all partition boundaries
— Burst Suspend Feature
— Enhanced Factory Programming at
3.1 µs/word (typ.for 0.13 µm)
Software
— 5 µs (typ.) Program and Erase Suspend
Latency Time
— Flash Data Integrator (FDI) and Common
Flash Interface (CFI) Compatible
— Programmable WAIT Signal Polarity
Security
Packaging and Power
— 128-bit Protection Register
— 0.13 µm: 32-, 64-, and 128-Mbit in VF
— 64-bits Unique Programmed by Intel
BGA Package; 128-Mbit in QUAD+
— 64-bits User-Programmable
Package
— Absolute Write Protection with VPP at
— 0.18 µm: 32- and 128-Mbit Densities in
Ground
VF BGA Package; 64-Mbit Density in
www.DataSheet4U.com—Individual and Instantaneous Block
Locking/Unlocking with Lock-Down
µBGA* Package
— 56 Active Ball Matrix, 0.75 mm Ball-
Capability
Pitch
Quality and Reliability
— Temperature Range: –40 °C to +85 °C
— 100k Erase Cycles per Block
— VCC = 1.70 V to 1.95 V
— VCCQ = 1.70 V to 2.24 V or 1.35 V to
1.80 V
— 0.13 µm ETOX™ VIII Process
— 0.18 µm ETOX™ VII Process
— Standby current (0.13 µm): 8µA (typ.)
— Read current: 7mA (typ.)
The Intel® Wireless Flash Memory (W18) device with flexible multi-partition dual operation,
provides high-performance asynchronous and synchronous burst reads. It is an ideal memory for
low-voltage burst CPUs. Combining high read performance with flash memory’s intrinsic non-
volatility, the W18 device eliminates the traditional system-performance paradigm of shadowing
redundant code memory from slow nonvolatile storage to faster execution memory. It reduces
the total memory requirement that increases reliability and reduces overall system power
consumption and cost.
The W18 device’s flexible multi-partition architecture allows programming or erasing to occur
in one partition while reading from another partition. This allows for higher data write
throughput compared to single partition architectures. The dual-operation architecture also
allows two processors to interleave code operations while program and erase operations take
place in the background. The designer can also choose the size of the code and data partitions via
the flexible multi-partition architecture.
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Notice: This document contains information on new products in production. The specifications
are subject to change without notice. Verify with your local Intel sales office that you have the
latest datasheet before finalizing a design.
290701-009
December 2003
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GE28F640W18 pdf
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Contents
Appendix C Mechanical Specifications.................................................................................95
Appendix D Ordering Information .........................................................................................100
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Datasheet
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GE28F640W18 arduino
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Intel® Wireless Flash Memory (W18)
partition boundaries, but user application code is responsible for ensuring that they don’t extend
into a partition that is actively programming or erasing. Although each partition has burst-read,
write, and erase capabilities, simultaneous operation is limited to write or erase in one partition
while other partitions are in a read mode.
Augmented erase-suspend functionality further enhances the RWW capabilities of this device. An
erase can be suspended to perform a program or read operation within any block, except that which
is erase-suspended. A program operation nested within a suspended erase can subsequently be
suspended to read yet another memory location.
After device power-up or reset, the W18 device defaults to asynchronous read configuration.
Writing to the device’s configuration register enables synchronous burst-mode read operation. In
synchronous mode, the CLK input increments an internal burst address generator. CLK also
synchronizes the flash memory with the host CPU and outputs data on every, or on every other,
valid CLK cycle after an initial latency. A programmable WAIT output signals to the CPU when
data from the flash memory device is ready.
In addition to its improved architecture and interface, the W18 device incorporates Enhanced
Factory Programming (EFP), a feature that enables fast programming and low-power designs. The
EFP feature provides the fastest currently-available program performance, which can increase a
factory’s manufacturing throughput.
The device supports read operations at 1.8 V and erase and program operations at 1.8 V or 12 V.
With the 1.8-V option, VCC and VPP can be tied together for a simple, ultra-low-power design. In
addition to voltage flexibility, the dedicated VPP input provides complete data protection when
VPP VPPLK.
www.DataSheet4U.comThis device allows I/O operation at voltages even lower than the minimum VCCQ of 1.7 V. This
Extended VCCQ range, 1.35 V – 1.8 V, permits even greater system design flexibility.
A 128-bit protection register enhances the user’s ability to implement new security techniques and
data protection schemes. Unique flash device identification and fraud-, cloning-, or content-
protection schemes are possible through a combination of factory-programmed and user-OTP data
cells. Zero-latency locking/unlocking on any memory block provides instant and complete
protection for critical system code and data. An additional block lock-down capability provides
hardware protection where software commands alone cannot change the block’s protection status.
The device’s Command User Interface (CUI) is the system processor’s link to internal flash
memory operation. A valid command sequence written to the CUI initiates device Write State
Machine (WSM) operation that automatically executes the algorithms, timings, and verifications
necessary to manage flash memory program and erase. An internal status register provides ready/
busy indication results of the operation (success, fail, and so on).
Three power-saving features– Automatic Power Savings (APS), standby, and RST#– can
significantly reduce power consumption. The device automatically enters APS mode following
read cycle completion. Standby mode begins when the system deselects the flash memory by
de-asserting CE#. Driving RST# low produces power savings similar to standby mode. It also
resets the part to read-array mode (important for system-level reset), clears internal status registers,
and provides an additional level of flash write protection.
Datasheet
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