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PDF W78E62B Data sheet ( Hoja de datos )
| Número de pieza | W78E62B | |
| Descripción | 8-Bit Microcontroller | |
| Fabricantes | Winbond | |
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W78E62B
8-BIT MICROCONTROLLER
GENERAL DESCRIPTION
The W78E62B is an 8-bit microcontroller which has an in-system programmable MTP-ROM for
firmware updating. The instruction set of the W78E62B is fully compatible with the standard 8052.
The W78E62B contains a 64K bytes of main MTP-ROM and a 4K bytes of auxiliary MTP-ROM which
allows the contents of the 64KB main MTP-ROM to be updated by the loader program located at the
4KB auxiliary MTP-ROM; 512 bytes of on-chip RAM; four 8-bit bi-directional and bit-addressable I/O
ports; an additional 4-bit port P4; three 16-bit timer/counters; a serial port. These peripherals are
supported by a eight sources two-level interrupt capability. To facilitate programming and verification,
the MTP-ROM inside the W78E62B allows the program memory to be programmed and read
electronically. Once the code is confirmed, the user can protect the code for security.
The W78E62B microcontroller has two power reduction modes, idle mode and power-down mode,
both of which are software selectable. The idle mode turns off the processor clock but allows for
continued peripheral operation. The power-down mode stops the crystal oscillator for minimum power
consumption. The external clock can be stopped at any time and in any state without affecting the
processor.
FEATURES
• Fully static design 8-bit CMOS microcontroller up to 40 MHz.
www.DataSheet4U.com• 64K bytes of in-system programmable MTP-ROM for Application Program (APROM).
• 4K bytes of auxiliary MTP-ROM for Loader Program (LDROM).
• Low standby current at full supply voltage.
• 512 bytes of on-chip RAM. (including 256 bytes of AUX-RAM, software selectable)
• 64K bytes program memory address space and 64K bytes data memory address space.
• Four 8-bit bi-directional ports.
• One 4-bit multipurpose programmable port.
• Build-in 74373 and 74244 logical functions on Port 2.(software programmable)
• Three 16-bit timer/counters
• One full duplex serial port
• Eight-sources, two-level interrupt capability
• Built-in power management
• Code protection
• PACKAGE
− PLCC 44: W78E62BP-40
− LQFP 48: W78E62BD-40
Publication Release Date: June 1999
- 1 - Revision A1
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1 page  
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W78E62B
FUNCTIONAL DESCRIPTION
The W78E62B architecture consists of a core controller surrounded by various registers, four general
purpose I/O ports, one special purpose programmable 4-bits I/O port, 512 bytes of RAM, three
timer/counters, a serial port, and an internal 74373 latch and 74244 buffer which can be switched to
port2. The processor supports 111 different opcodes and references both a 64K program address
space and a 64 K data storage space.
RAM
The internal data RAM in the W78E62B is 512 bytes. It is divided into two banks: 256 bytes of
scratchpad RAM and 256 bytes of AUX-RAM. These RAMs are addressed by different ways.
• RAM 0H−127H can be addressed directly and indirectly as the same as in 8051. Address pointers
are R0 and R1 of the selected register bank.
• RAM 128H−255H can only be addressed indirectly as the same as in 8051. Address pointers are
R0, R1 of the selected registers bank.
• AUX-RAM 0H−255H is addressed indirectly as the same way to access external data memory with
the MOVX instruction. Address pointer are R0 and R1 of the selected register bank and DPTR
register. An access to external data memory locations higher than 255H will be performed with the
MOVX instruction in the same way as in the 8051. The AUX-RAM is disable after a reset. Setting
the bit 4 in CHPCON register will enable the access to AUX-RAM. When AUX-RAM is enabled the
www.DataSheet4U.cominstructions of "MOVX @Ri" will always access to on-chip AUX-RAM. When executing from
internal program memory, an access to AUX-RAM will not affect the Ports P0, P2, WR and RD .
Timers 0, 1, and 2
Timers 0, 1, and 2 each consist of two 8-bit data registers. These are called TL0 and TH0 for Timer 0,
TL1 and TH1 for Timer 1, and TL2 and TH2 for Timer 2. The TCON and TMOD registers provide
control functions for timers 0, 1. The T2CON register provides control functions for Timer 2. RCAP2H
and RCAP2L are used as reload/capture registers for Timer 2.
The operations of Timer 0 and Timer 1 are the same as in the W78C51. Timer 2 is a 16-bit
timer/counter that is configured and controlled by the T2CON register. Like Timers 0 and 1, Timer 2
can operate as either an external event counter or as an internal timer, depending on the setting of bit
C/T2 in T2CON. Timer 2 has three operating modes: capture, auto-reload, and baud rate generator.
The clock speed at capture or auto-reload mode is the same as that of Timers 0 and 1.
INT2 / INT3
Two additional external interrupts, INT2 and INT3 , whose functions are similar to those of external
interrupt 0 and 1 in the standard 80C52. The functions/status of these interrupts are
determined/shown by the bits in the XICON (External Interrupt Control) register. The XICON register
is bit-addressable but is not a standard register in the standard 80C52. Its address is at 0C0H. To
set/clear bits in the XICON register, one can use the "SETB ( CLR ) bit" instruction. For example,
"SETB 0C2H" sets the EX2 bit of XICON.
Publication Release Date: June 1999
- 5 - Revision A1
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5 Page 
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W78E62B
P2EAH, P2EAL:
The Port Enable Address Registers for Port2 as an Input Buffer/Output-Latched Port.
The I/O port enable address is need to assign when Port2 is defined as input buffer like a 74244, or a
output-latched logic like a 74373. The P2EAH contains the high-order byte of address, the P2EAL
contains the low-order byte of address. The following example shows how to program the Port 2 as a
output-latched port at address 5678H.
MOV P2EAL,#78H
; High-order byte of address to enable Port2 latch function.
MOV P2EAH,#56H
; Low-order byte of address to enable Port2 latch function.
MOV P2ECON,#02H
; Configure the Port2 as an output-latched port.
MOV DPTR,#5678H
; Move data 5678H to DPTR.
MOV A, #55H
MOVX @DPTR, A
; The pins P2.7−P2.0 will output and latch the value 55H.
When Port2 is configured as 74244 or 74373 function, the instruction " MOV P2,#XX " will write the
data #XX to P2 register only but not output to port pins P2.7−P2.0.
Port 2 Expanded Control Register(P2ECON).
P2ECON (AEHw) ww.DataSheet4U.com
BIT NAME
FUNCTION
7 P43CSINV The active polarity of P4.3 when pin P4.3 is defined as read and/or write
strobe signal.
= 1 : P4.3 is active high when pin P4.3 is defined as read and/or write strobe
signal.
= 0 : P4.3 is active low when pin P4.3 is defined as read and/or write strobe
signal.
6 P42CSINV The similarity definition as P43SINV.
5 P41CSINV The similarity definition as P43SINV.
4 P40CSINV The similarity definition as P43SINV.
3 - Reserve
2 - Reserve
1, 0 P2CN1, 00 : Pins P2.7−P2.0 is the standard 8051 Port 2.
P2CN0 01 : Pins P2.7−P2.0 is input buffer port which the port enable address
depends on the content of P2EAL and P2EAH
10 : Pins P2.7−P2.0 is output-latched port which the port enable address
depends on the content of P2EAL and P2EAH.
11 : Undefined.
- 11 -
Publication Release Date: June 1999
Revision A1
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