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PDF P6NA60FI Data sheet ( Hoja de datos )

Número de pieza P6NA60FI
Descripción STP6NA60FI
Fabricantes ST Microelectronics 
Logotipo ST Microelectronics Logotipo



Total 10 Páginas
		
P6NA60FI Hoja de datos, Descripción, Manual
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STP6NA60
STP6NA60FI
N - CHANNEL ENHANCEMENT MODE
FAST POWER MOS TRANSISTOR
TYPE
ST P 6NA 60
ST P 6NA 60 F I
VDSS
600 V
600 V
R DS( on)
< 1.2
< 1.2
ID
6.5 A
3.9 A
s TYPICAL RDS(on) = 1
s ± 30V GATE TO SOURCE VOLTAGE RATING
s 100% AVALANCHE TESTED
s REPETITIVE AVALANCHE DATA AT 100oC
s LOW INTRINSIC CAPACITANCES
s GATE GHARGE MINIMIZED
s REDUCED THRESHOLD VOLTAGE SPREAD
DESCRIPTION
This series of POWER MOSFETS represents the
most advanced high voltage technology. The
optimized cell layout coupled with a new
proprietary edge termination concur to give the
device low RDS(on) and gate charge, unequalled
ruggedness and superior switching performance.
APPLICATIONS
s HIGH CURRENT, HIGH SPEED SWITCHING
s SWITCH MODE POWER SUPPLIES (SMPS)
s DC-AC CONVERTERS FOR WELDING
EQUIPMENT AND UNINTERRUPTIBLE
POWER SUPPLIES AND MOTOR DRIVE
ABSOLUTE MAXIMUM RATINGS
Symbol
P ar amete r
VD S Drain-source Voltage (VGS = 0)
VDG R Drain-gate Voltage (RG S = 20 k)
VGS Gate-source Voltage
ID Drain Current (continuous) at T c = 25 oC
ID Drain Current (continuous) at T c = 100 oC
IDM() Drain Current (pulsed)
Ptot Total Dissipation at Tc = 25 oC
Derating Factor
VISO Insulation Withstand Voltage (DC)
Tstg Storage Temperature
Tj Max. Operating Junction Temperature
() Pulse width limited by safe operating area
November 1996
3
2
1
TO-220
3
2
1
ISOWATT220
INTERNAL SCHEMATIC DIAGRAM
Val ue
STP6NA60
STP6NA60FI
600
600
± 30
6.5 3.9
4.3 2.6
26 26
125 45
1 0.36
2000
-65 to 150
150
Unit
V
V
V
A
A
A
W
W/oC
V
oC
oC
1/10

1 page

P6NA60FI pdf
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Transconductance
STP6NA60/FI
Static Drain-source On Resistance
Gate Charge vs Gate-source Voltage
Capacitance Variations
Normalized Gate Threshold Voltage vs
Temperature
Normalized On Resistance vs Temperature
5/10

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