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Número de pieza | EP2C50 | |
Descripción | ISDN Line Interface | |
Fabricantes | Altera | |
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Section IV. I/O Standards
This section provides information on Cyclone™ II single-ended, voltage
referenced, and differential I/O standards.
This section includes the following chapters:
■ Chapter 10, Selectable I/O Standards in Cyclone II Devices
■ Chapter 11, High-Speed Differential Interfaces in Cyclone II Devices
Revision History The table below shows the revision history for Chapters 10 and 11.
Chapter(s) Date / Version
Changes Made
10 November 2004, Updated Table 10–7.
v1.1
www.DataSheet4U.comJune 2004, v1.0 Added document to the Cyclone II Device
Handbook.
11 November 2004, ● Updated Table 11–1.
v1.1 ● Updated Figures 11–4, 11–5, 11–7, and
11–8.
June 2004, v1.0 Added document to the Cyclone II Device
Handbook.
Altera Corporation
Section IV–1
Preliminary
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1 page www.DataSheet4U.com
Selectable I/O Standards in Cyclone II Devices
Table 10–1. Cyclone II Supported I/O Standards & Constraints (Part 2 of 2)
I/O Standard
Differential HSTL-15 class I
or class II
Differential HSTL-18 class I
or class II
LVDS
RSDS and mini-LVDS (7)
LVPECL (8)
Type
Pseudo
differential (3)
Pseudo
differential (3)
Differential
Differential
Differential
VCCIO Level
Top & Bottom
I/O Pins
Side I/O Pins
Input
Output
CLK,
DQS
User I/O
Pins
CLK,
DQS
PLL_OUT
User I/O
Pins
(4) 1.5 V
v (6)
1.5 V (4) v
(5)
v
(5)
(4) 1.8 V
v (6)
1.8 V (4) v
(5)
v
(5)
2.5 V 2.5 V v v v
v
v
(4) 2.5 V
v
vv
3.3 V/ (4)
2.5 V/
1.8 V/
v
1.5 V
v
Notes to Table 10–1:
(1) These pins support SSTL-18 class II and 1.8- and 1.5-V HSTL class II inputs.
www.DataSheet4U.com(2) PCI-X does not meet the IV curve requirement at the linear region. PCI-clamp diode is not available on top and
bottom I/O pins.
(3) Pseudo-differential HSTL and SSTL outputs use two single-ended outputs with the second output programmed
as inverted. Pseudo-differential HSTL and SSTL inputs treat differential inputs as two single-ended HSTL and
SSTL inputs and only decode one of them.
(4) This I/O standard is not supported on these I/O pins.
(5) This I/O standard is only supported on the dedicated clock pins.
(6) PLL_OUT does not support differential SSTL-18 class II and differential 1.8 and 1.5-V HSTL class II.
(7) mini-LVDS and RSDS are only supported on output pins.
(8) LVPECL is only supported on clock inputs.
3.3-V LVTTL (EIA/JEDEC Standard JESD8-B)
The 3.3-V LVTTL I/O standard is a general-purpose, single-ended
standard used for 3.3-V applications. The LVTTL standard defines the DC
interface parameters for digital circuits operating from a 3.0-/3.3-V
power supply and driving or being driven by LVTTL-compatible devices.
The LVTTL input standard specifies a wider input voltage range of
– 0.3 V ≤ VI ≤ 3.9 V. Altera recommends an input voltage range of
– 0.5 V ≤ VI ≤ 4.1 V.
Altera Corporation
November 2004
Preliminary
10–3
Cyclone II Device Handbook, Volume 1
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5 Page www.DataSheet4U.com
Selectable I/O Standards in Cyclone II Devices
Figure 10–4. SSTL-2 Class II Differential Termination
VTT = 1.25 V VTT = 1.25 V
VTT = 1.25 V VTT = 1.25 V
Differential
Transmitter
50 Ω
25 Ω
50 Ω
50 Ω
Z0 = 50 Ω
50 Ω
Differential
Receiver
25 Ω
Z0 = 50 Ω
1.8-V LVTTL Normal & Wide Voltage Ranges (EIA/JEDEC
Standard EIA/JESD8-7)
The 1.8-V I/O standard is used for 1.8-V LVTTL applications. This
standard defines the DC interface parameters for high-speed, low-
voltage, non-terminated digital circuits driving or being driven by other
www.DataSheet4U.com1.8-V parts. The input and output voltage ranges are:
■ The 1.8-V normal and wide range input standards specify an input
voltage range of – 0.3 V × VI ≤ 2.25 V.
■ The normal range minimum VOH requirement is VCCIO – 0.45 V.
■ The wide range minimum VOH requirement is VCCIO – 0.2 V.
The 1.8-V standard does not require input reference voltages or board
terminations. Cyclone II devices support input and output levels for both
normal and wide 1.8-V LVTTL ranges.
1.8-V LVCMOS Normal & Wide Voltage Ranges (EIA/JEDEC
Standard EIA/JESD8-7)
The 1.8-V I/O standard is used for 1.8-V LVCMOS applications. This
standard defines the DC interface parameters for high-speed, low-
voltage, non-terminated digital circuits driving or being driven by other
1.8-V parts. The input and output voltage ranges are:
■ The 1.8-V normal and wide range input standards specify an input
voltage range of – 0.3 V ≤ VI ≤ 2.25 V.
■ The normal range minimum VOH requirement is VCCIO – 0.45 V.
■ The wide range minimum VOH requirement is VCCIO – 0.2 V.
Altera Corporation
November 2004
Preliminary
10–9
Cyclone II Device Handbook, Volume 1
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11 Page |
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