DataSheet.es    


PDF DM81LS97A Data sheet ( Hoja de datos )

Número de pieza DM81LS97A
Descripción (DM81LS95A - DM81LS97A) 3-STATE Octal Buffer
Fabricantes Fairchild Semiconductor 
Logotipo Fairchild Semiconductor Logotipo



Hay una vista previa y un enlace de descarga de DM81LS97A (archivo pdf) en la parte inferior de esta página.


Total 7 Páginas

No Preview Available ! DM81LS97A Hoja de datos, Descripción, Manual

www.DataSheet4U.com
September 1991
Revised May 1999
DM81LS95A • DM81LS96A • DM81LS97A
3-STATE Octal Buffer
General Description
These devices provide eight, two-input buffers in each
package. All employ low-power-Schottky TTL technology.
One of the two inputs to each buffer is used as a control
line to gate the output into the high-impedance state, while
the other input passes the data through the buffer. The
DM81LS95A and DM81LS97A present true data at the out-
puts, while the DM81LS96A is inverting. On the
DM81LS95A and DM81LS96A versions, all eight 3-STATE
enable lines are common, with access through a 2-input
NOR gate. On the DM81LS97A version, four buffers are
enabled from one common line, and the other four buffers
are enabled form another common line. In all cases the
outputs are placed in the 3-STATE condition by applying a
high logic level to the enable pins.
Features
s Typical power dissipation
DM81LS95A, DM81LS97A 80 mW
DM81LS96A
s Typical propagation delay
65 mW
DM81LS95A, DM81LS97A 15 ns
DM81LS96A
10 ns
s Low power-Schottky, 3-STATE technology
Ordering Code:
Order Number Package Number
Package Description
www.DataSheet4U.comDM81LS95AWM
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
DM81LS95AN
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
DM81LS96AWM
DM81LS96AN
DM81LS97AN
M20B
N20A
N20A
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
DM81LS95A and DM92LS96A
Pin Names
Descriptions
A1–A8
Y1–Y8
Inputs
Outputs
G1–G2
Active LOW Output Enables (Note 1)
Note 1: Both G1 and G2 must be LOW for outputs to be enabled.
DM81LS97A
Pin Names
Descriptions
A1–A8
Inputs
Y1–Y8
Outputs
G1 Active LOW Output Enable (Y1–Y4)
G2 Active LOW Output Enable (Y5–Y8)
© 1999 Fairchild Semiconductor Corporation DS006435
www.fairchildsemi.com
www.DataSheet4U.com

1 page




DM81LS97A pdf
www.DataSheet4U.com
DC Electrical Characteristics DM81LS96A
over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Typ
Min Max
(Note 8)
Units
VI Input Clamp Voltage
VOH HIGH Level Output Voltage
VOL LOW Level Output Voltage
II Input Current @ Max
Input Voltage
VCC = Min, II = −18 mA
VCC = Min, IOH = Max
VIL = Max, VIH = Min
VCC = Min, IOL = Max
IOL = Max, VIH = Min
IOL = 12 mA, VCC = Min
VCC = Max, VI = 7V
1.5
V
2.7 V
0.5
V
0.4
0.1 mA
IIH HIGH Level Input Current
IIL LOW Level Input Current
VCC = Max, VI = 2.7V
VCC = Max VI = 0.5V
VI = 0.4V
A (Note 9)
A (Note 10)
20 µA
20
50 µA
G 50
IOZH
Off-State Output Current
with HIGH Level Output
Voltage Applied
VCC = Max, VO = 2.4V
VIH = Min, VIL = Max
20 µA
IOZL Off-State Output Current
with LOW Level Output
Voltage Applied
VCC = Max, VO = 0.4V
VIH = Min, VIL = Max
20 µA
IOS Short Circuit
Output Current
VCC = Max
(Note 11)
20
100
mA
ICC Supply Current
VCC = Max (Note 10)
13 21
Note 8: All typicals are at VCC = 5V, TA = 25°C.
Note 9: Both G inputs are at 2V.
Note 10: Both G inputs are at 0.4V.
www.DataSheet4U.comNote 11: Not more than one output should be shorted at a time, and the duration should not exceed one second.
mA
AC Electrical Characteristics DM81LS96A
VCC = 5V, TA = 25°C
RL = 667
Symbol
Parameter
CL = 50 pF
CL = 150 pF
Units
Min Max Min Max
tPLH Propagation Delay Time
LOW-to-HIGH Level Output
10 16 ns
tPHL Propagation Delay Time
HIGH-to-LOW Level Output
17 30 ns
tPZH Output Enable Time
to HIGH Level Output
15 30 ns
tPZL Output Enable Time
to LOW Level Output
35 45 ns
tPHZ Output Disable Time
from HIGH Level Output (Note 12)
20 ns
tPLZ Output Disable Time
from LOW Level Output (Note 12)
27 ns
Note 12: CL = 5 pF.
5 www.fairchildsemi.com
www.DataSheet4U.com

5 Page










PáginasTotal 7 Páginas
PDF Descargar[ Datasheet DM81LS97A.PDF ]




Hoja de datos destacado

Número de piezaDescripciónFabricantes
DM81LS97A(DM81LS95A - DM81LS97A) 3-STATE Octal BufferFairchild Semiconductor
Fairchild Semiconductor
DM81LS97A(DM81LS95A - DM81LS98A) TRI-STATE Octal BufferNational Semiconductor
National Semiconductor

Número de piezaDescripciónFabricantes
SLA6805M

High Voltage 3 phase Motor Driver IC.

Sanken
Sanken
SDC1742

12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.

Analog Devices
Analog Devices


DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.


DataSheet.es    |   2020   |  Privacy Policy  |  Contacto  |  Buscar