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PDF DM8108 Data sheet ( Hoja de datos )
| Número de pieza | DM8108 | |
| Descripción | 8 port 10/100M Fast Ethernet Switching Controller | |
| Fabricantes | Davicom | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de DM8108 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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DM8108
8 port 10/100M Fast Ethernet Switching Controller
General Description
The DM8108 is an 8 port 10/100Mbit/s nonblocking
Ethernet switch with on-chip address-lookup engine. The
DM8108 provides a low-cost, high-performance switch
solution with PHYs and single SGRAM.
The DM8108 provides eight 10/100Mbit/s Fast Ethernet
interface. In half-duplex mode, all ports support back-
pressure capability to reduce the risk of data loss for a long
burst of activity. In the full-duplex mode of operation, the
device uses IEEE std. 802.3 frame-based pause protocol
for flow control. With full-duplex capability, port 0 – 7 support
1.6Gbit/s aggregate bandwidth connections. The DM8108
also supports port trunking/load balancing on the
10/100Mbit ports. This can be used to group ports on inter-
switch links to increase the effective bandwidth between the
systems.
The internal address-lookup engine supports up to 16.25K
unicast and unlimited multicast and broadcast addresses.
This engine performs destination and source addresses
book-keeping and comparison which also forwards
unknown destination address packets to all ports.
The DM8108 is fabricated with a .35um technology.
Working at 3.3V, the inputs are 5V tolerant and the outputs
are capable of directly driving at TTL levels.
Block Diagram
Control &
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Address
Learning
Expansion
MEM
Controller
Switching
Engine
LED Control
Unit
Preliminary
Version: DM8108-DS-P02
November 25, 1999
1
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1 page  
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Pin Configuration
DM8108
8 port 10/100M Fast Ethernet Switching Controller
VSS
LEDCLK
LEDSTB
LEDD
RST#
TESTEN
VSS
RXER0
RXDV0
COL0
CRS0
RXCLK0
RXD0[0]
RXD0[1]
RXD0[2]
RXD0[3]
TXCLK0
TXEN0
TXD0[0]
TXD0[1]
TXD0[2]
TXD0[3]
VDD
RXER1
RXDV1
COL1
CRS1
RXCLK1
RXD1[0]
RXD1[1]
RXD1[2]
RXD1[3]
TXCLK1
TXEN1
TXD1[0]
TXD1[1]
TXD1[2]
TXD1[3]
VSS
RXER2
RXDV2
COL2
CRS2
RXCLK2
RXD2[0]
RXD2[1]
RXD2[2]
RXD2[3]
TXCLK2
TXEN2
TXD2[0]
TXD2[1]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
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130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
VDD
DMD16
DMD17
DMD18
DMD19
DMD20
DMD21
DMD22
DMD23
VSS
DMD24
DMD25
DMD26
DMD27
DMD28
DMD29
DMD30
DMD31
VSS
TXD7[3]
TXD7[2]
TXD7[1]
TXD7[0]
TXEN7
TXCLK7
RXD7[3]
RXD7[2]
RXD7[1]
RXD7[0]
RXCLK7
CRS7
COL7
RXDV7
RXER7
VDD
TXD6[3]
TXD6[2]
TXD6[1]
TXD6[0]
TXEN6
TXCLK6
RXD6[3]
RXD6[2]
RXD6[1]
RXD6[0]
RXCLK6
CRS6
COL6
RXDV6
RXER6
VSS
TXD5[3]
Preliminary
Version: DM8108-DS-P02
November 25, 1999
5
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DM8108
8 port 10/100M Fast Ethernet Switching Controller
Packet Routing
As any port in the DM8108 receives a packet, the DM8108
will put the received data in the receiving buffer and start the
address recognition at same time.
The DM8108 is targeted for the non-managed Ethernet
Switching application. No management functions provided.
DRAM Interface
1. If the destination address is pointed to a local port
The DM8108 interfaces to 1M or 2M bytes of SGRAM or
other than receiving port, the DM8108 will update the
SDRAM. The DRAM is used to store incoming packets as
Transmit Descriptor of the target port with the buffer
well as he address table and Transmit Descriptors. The
location and byte count information and wait for
DRAM can operate at up to 90MHz. One 256kx32 or
transmission.
512kx16 SGRAM are required respectively for 1M or 2M
2. If the destination address is pointed to a port located in shared memory size.
other devices, the DM8108 will update the
Transmit Descriptor of the expansion port with the
receiving buffer location and byte count information
Expansion Bus
and wait for transmission.
3. The expansion bus contains Receive Port and Transmit I
f the destination address is not found in the Address
Port. Each port is 4-bit wide.
Table, the DM8108 will update all the Transmit
Descriptors, except the one of the receiving port, for
The Receive Port takes the incoming packet into a FIFO
transmission.
that has to be distributed to the Receiving Buffer
4. For the Multicast/Broadcast addresses, the DM8108
immediately. At the same time, the DM8108 will check the
simply updates all the Transmit Descriptors, except
destination and source addresses to determine the target
the one of the receiving port or the ports that are
www.DataSheet4U.comdisabled, forTransmission.
port and update the Address Table if necessary.
5. For bad packet, the DM8108 simply discards it.
The Transmit Port is dedicated for transferring packets out
6. If the receiving buffer or the Transmit Descriptor for a
to other switching members if the Transmit Descriptor for
particular port is full, the packet will be lost.
this port saying the transmission is pending.
Network Management Features
Total of 8-DM8108 can be cascaded for a 64-port switching
system.
Preliminary
Version: DM8108-DS-P02
November 25, 1999
11
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet DM8108.PDF ] | |
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