DataSheet.es    


PDF FAN5078 Data sheet ( Hoja de datos )

Número de pieza FAN5078
Descripción DDR/ACPI Regulator Combo
Fabricantes Fairchild Semiconductor 
Logotipo Fairchild Semiconductor Logotipo



Hay una vista previa y un enlace de descarga de FAN5078 (archivo pdf) en la parte inferior de esta página.


Total 16 Páginas

No Preview Available ! FAN5078 Hoja de datos, Descripción, Manual

www.DataSheet4U.com
May 2006
FAN5078
DDR/ACPI Regulator Combo
Features
ƒ PWM regulator for VDDQ (2.5V or 1.8)
ƒ Linear LDO regulator generates VTT = VDDQ/2,
1.5A Peak sink/source capability
ƒ AMT / M-state support
ƒ Control to generate 5V USB
ƒ ACPI drive and control for 5V DUAL generation
ƒ 3.3V internal LDO for 3V-ALW generation
ƒ 300 kHz fixed frequency switching
ƒ RDS(ON) current sensing or optional current sense resistor
for precision over-current detect
ƒ Internal synchronous boot diode
ƒ Common Power Good signal for all voltages
ƒ Input under-voltage lockout (UVLO)
ƒ Thermal shutdown
ƒ Latched multi-fault protection
ƒ Precision reference output for ULDO controllers
ƒ 24-pin 5 x 5 MLP package
Applications
ƒ DDR VDDQ and VTT voltage generation with ACPI
support
ƒ Desktop PC's
ƒ Servers
Description
The FAN5078 DDR memory regulator combines a high-
efficiency Pulse-Width Modulated (PWM) controller to
generate the memory supply voltage, VDDQ, and a linear
regulator to generate termination voltage (VTT).
Synchronous rectification provides high efficiency over a wide
range of load currents. Efficiency is further enhanced by using
the low-side MOSFET’s RDS(ON) to sense current.
The VDDQ PWM regulator is a sampled current mode control
with external compensation to achieve fast load-transient
response and provide system design optimization.
The VTT regulator derives its reference and takes its power
from the VDDQ PWM regulator, output. The VTT termination
regulator is capable of sourcing or sinking 1.5A peak currents.
In S5 M1 mode, the VDDQ switcher, VTT regulator, and the
3.3V regulators remain on. S3 mode keeps these regulators
on, but also turns on an external P-Channel to provide 5V
USB.
A single soft-start capacitor enables controlled slew rates for
both VDDQ and 3.3V-ALW outputs.
PGOOD becomes true in S0 only after all regulators have
achieved stable outputs.
In S5 (EN = 0), the 3.3V internal LDO stays on while the other
regulators are powered down.
Ordering Information
Part Number
FAN5078MPX
Temperature Range
-10°C to 85°C
Package
MLP-24 5x5mm
Packing
Tape and Reel
© 2006 Fairchild Semiconductor Corporation
FAN5078 Rev. 1.0.0 • 05/09/06
www.fairchildsemi.com

1 page




FAN5078 pdf
www.DataSheet4U.com
Pin Configuration
SBUSB#
S4ST#
SBSW
5V MAIN
VTT SNS
VTT OUT
24 23 22 21 20 19
P1 = GND
7 8 9 10 11 12
EN
S3#I
S3#O
3.3 ALW
VCC
PGOOD
FAN5078MP 5x5mm MLP package (θJA = 38°C/W)
Note: Connect P1 pad to GND.
Pin Definitions
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Pin
SBUSB#
S4ST#
SBSW
5V MAIN
VTT SNS
VTT OUT
VDDQ IN
BOOT
HDRV
SW
ISNS
LDRV
PGOOD
VCC
Pin Function Description
USB Standby. Pulls low with constant current to limit slew rate in S3 if S4ST# is high. Drives a P-
Channel MOSFET to connect 5VSB to 5V USB.
S4_STATE# Connect to system logic signal that enables 5V USB power in S3.
Standby Switch. Drives the P-Channel MOSFET to power 5V DUAL from 5VSB when in S3. High in
S0 and S5.
5V MAIN. When this pin is below 4.5V, transition from S3 to S0 is inhibited.
VTT remote sense input.
VTT regulator power output.
VDDQ Input from PWM. Connect to VDDQ output voltage. This is the VTT Regulator power input.
Boot. Positive supply for the upper MOSFET driver. Connect as shown in Figure 1. IC contains a boot
diode to VCC.
High-Side Drive. High-side (upper) MOSFET driver output. Connect to gate of high-side MOSFET.
Switching Node. Return for the high-side MOSFET driver and a current sense input. Connect to
source of high-side MOSFET and low-side MOSFET drain.
Current Sense Input. Monitors the voltage drop across the lower MOSFET or external sense resistor
for current feedback and current limiting.
Low-Side Drive The low-side (lower) MOSFET driver output. Connect to gate of low-side MOSFET.
Power Good Flag. An open-drain output that pulls LOW when FB is outside of a ±10% range of the
0.9V reference or the VTT output is < 80% or > 110% of its reference. PGOOD goes low when the IC
is in the S5 state. The power-good signal from the PWM regulator enables the VTT regulator.
VCC. Provides IC bias and gate drive power. The IC is held in standby until this pin is above the UVLO
threshold.
© 2006 Fairchild Semiconductor Corporation
FAN5078 Rev. 1.0.0 • 05/11/06
5
www.fairchildsemi.com

5 Page





FAN5078 arduino
www.DataSheet4U.com
5V SB
V(UVLO)
SS
4V
3.8V
1V
VDDQ
3.3V LDO
T0 T1 T2 T3 T4 T5
Figure 8. Start-up Sequence into S0
PWM Regulator
A PSPICE model and spreadsheet calculator are available
in Application Note AN-6006 for the VDDQ PWM regulator
to select external components and verify loop stability. The
topics covered below provide the explanation behind the
calculations in the spreadsheet.
Setting the Output Voltage
The output voltage of the PWM regulator can be set in the
range of 0.9V to 80% of its power input by an external
resistor divider.
The internal reference is 0.9V. The output is divided down
by an external voltage divider to the FB pin (for example, R1
and R2 in Figure 1). There is also a 1.3μA current sourced
out of FB to ensure that if the pin is open, VDDQ remains
low. The output voltage therefore is:
0.9V
R2
=
VOUT 0.9V
R1
+ 1.3μA
(3a)
To minimize noise pickup on this node, keep the resistor to
GND (R2) below 2K. In the example below, R2 is 1.82K and
R1 is calculated:
R1 =
R2 (VOUT 0.9)
0.9 1.3μA
=
1.815K 1.82K
(3b)
The synchronous buck converter is optimized for 5V input
operation. The PWM modulator uses an average current
mode control for simplified feedback loop compensation.
Oscillator
The oscillator frequency is 300Khz. The internal PWM ramp
is reset on the rising clock edge.
PWM Soft Start
When the PWM regulator is enabled, the circuit waits until
the VDDQ IN pin is below 100mV to ensure that the soft-
start cycle does not begin with a large residual voltage on
the PWM regulator output.
When the PWM regulator is disabled, 40Ω is connected
from VDDQ IN to PGND to discharge the output. The circuit
waits until the FB pin is below 100mV to ensure that the
soft-start cycle does not begin with a large residual voltage
on the VDDQ regulator output.
The voltage at the positive input of the error amplifier is
limited to VCSS, which is charged with about 45μA. Once CSS
has charged to 0.9V, the output voltage is in regulation.
© 2006 Fairchild Semiconductor Corporation
FAN5078 Rev. 1.0.0 • 05/11/06
11
www.fairchildsemi.com

11 Page







PáginasTotal 16 Páginas
PDF Descargar[ Datasheet FAN5078.PDF ]




Hoja de datos destacado

Número de piezaDescripciónFabricantes
FAN5070High Performance Programmable Synchronous DC-DC ControllerFairchild Semiconductor
Fairchild Semiconductor
FAN5071High Performance Programmable Synchronous DC-DC Controller for Multi-Voltage PlatformsFairchild Semiconductor
Fairchild Semiconductor
FAN5078DDR/ACPI Regulator ComboFairchild Semiconductor
Fairchild Semiconductor

Número de piezaDescripciónFabricantes
SLA6805M

High Voltage 3 phase Motor Driver IC.

Sanken
Sanken
SDC1742

12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.

Analog Devices
Analog Devices


DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.


DataSheet.es    |   2020   |  Privacy Policy  |  Contacto  |  Buscar