|
|
PDF 29LV400BMC Data sheet ( Hoja de datos )
| Número de pieza | 29LV400BMC | |
| Descripción | MX29LV400BMC | |
| Fabricantes | Macronix International | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de 29LV400BMC (archivo pdf) en la parte inferior de esta página. Total 59 Páginas | ||
|
No Preview Available !
www.DataSheet4U.com
MX29LV400T/B
FEATURES
4M-BIT [512K x 8 / 256K x 16] CMOS SINGLE VOLTAGE
3V ONLY FLASH MEMORY
• Extended single - supply voltage range 2.7V to 3.6V
• 524,288 x 8/262,144 x 16 switchable
• Single power supply operation
- 3.0V only operation for read, erase and program
operation
• Fast access time: 55R/70/90ns
www.DataSheet•4UL.coomw power consumption
- 20mA maximum active current
- 0.2uA typical standby current
• Command register architecture
- Byte/word Programming (9us/11us typical)
- Sector Erase (Sector structure 16K-Byte x 1,
8K-Byte x 2, 32K-Byte x1, and 64K-Byte x7)
• Auto Erase (chip & sector) and Auto Program
- Automatically erase any combination of sectors with
Erase Suspend capability.
- Automatically program and verify data at specified
address
• Erase suspend/Erase Resume
- Suspends sector erase operation to read data from,
or program data to, any sector that is not being erased,
then resumes the erase.
GENERAL DESCRIPTION
• Status Reply
- Data polling & Toggle bit for detection of program and
erase operation completion.
• Ready/Busy pin (RY/BY)
- Provides a hardware method of detecting program or
erase operation completion.
• Sector protection
- Hardware method to disable any combination of
sectors from program or erase operations
- Tempoary sector unprotect allows code changes in
previously locked sectors.
• 100,000 minimum erase/program cycles
• Latch-up protected to 100mA from -1V to VCC+1V
• Boot Sector Architecture
- T = Top Boot Sector
- B = Bottom Boot Sector
• Low VCC write inhibit is equal to or less than 2.3V
• Package type:
- 44-pin SOP
- 48-pin TSOP
- 48-ball CSP
• Compatibility with JEDEC standard
- Pinout and software compatible with single-power
supply Flash
The MX29LV400T/B is a 4-mega bit Flash memory or-
ganized as 512K bytes of 8 bits or 256K words of 16
bits. MXIC's Flash memories offer the most cost-effec-
tive and reliable read/write non-volatile random access
memory. The MX29LV400T/B is packaged in 44-pin
SOP, 48-pin TSOP and 48-ball CSP. It is designed to be
reprogrammed and erased in system or in standard
EPROM programmers.
mThe standard MX29LV400T/B offers access time as fast
oas 55ns, allowing operation of high-speed microproces-
.csors without wait states. To eliminate bus contention,
the MX29LV400T/B has separate chip enable (CE) and
Uoutput enable (OE) controls.
et4MXIC's Flash memories augment EPROM functionality
ewith in-circuit electrical erasure and programming. The
hMX29LV400T/B uses a command register to manage
Sthis functionality. The command register allows for 100%
taTTL level control inputs and fixed power supply levels
during erase and programming, while maintaining maxi-
amum EPROM compatibility.
www.DP/N:PM0710
1
MXIC Flash technology reliably stores memory contents
even after 100,000 erase and program cycles. The MXIC
cell is designed to optimize the erase and programming
mechanisms. In addition, the combination of advanced
tunnel oxide processing and low internal electric fields
for erase and program operations produces reliable cy-
cling. The MX29LV400T/B uses a 2.7V~3.6V VCC sup-
ply to perform the High Reliability Erase and auto Pro-
gram/Erase algorithms.
The highest degree of latch-up protection is achieved
with MXIC's proprietary non-epi process. Latch-up pro-
tection is proved for stresses up to 100 milliamps on
address and data pin from -1V to VCC + 1V.
REV. 1.4, NOV. 23, 2001
1 page  
www.DataSheet4U.com
MX29LV400T/B
AUTOMATIC PROGRAMMING
The MX29LV400T/B is byte programmable using the Au-
tomatic Programming algorithm. The Automatic Pro-
gramming algorithm makes the external system do not
need to have time out sequence nor to verify the data
programmed. The typical chip programming time at room
temperature of the MX29LV400T/B is less than 10 sec-
onds.
www.DataSheet4U.com
AUTOMATIC CHIP ERASE
The entire chip is bulk erased using 10 ms erase pulses
according to MXIC's Automatic Chip Erase algorithm.
Typical erasure at room temperature is accomplished in
less than 25 second. The Automatic Erase algorithm
automatically programs the entire array prior to electri-
cal erase. The timing and verification of electrical erase
are controlled internally within the device.
AUTOMATIC ERASE ALGORITHM
MXIC's Automatic Erase algorithm requires the user to
write commands to the command register using stan-
dard microprocessor write timings. The device will auto-
matically pre-program and verify the entire array. Then
the device automatically times the erase pulse width,
provides the erase verification, and counts the number
of sequences. A status bit toggling between consecu-
tive read cycles provides feedback to the user as to the
status of the erasing operation.
Register contents serve as inputs to an internal state-
machine which controls the erase and programming cir-
cuitry. During write cycles, the command register inter-
nally latches address and data needed for the program-
ming and erase operations. During a system write cycle,
addresses are latched on the falling edge, and data are
latched on the rising edge of WE or CE, whichever hap-
pens first.
AUTOMATIC SECTOR ERASE
The MX29LV400T/B is sector(s) erasable using MXIC's
Auto Sector Erase algorithm. The Automatic Sector
Erase algorithm automatically programs the specified
sector(s) prior to electrical erase. The timing and verifi-
cation of electrical erase are controlled internally within
the device. An erase operation can erase one sector,
multiple sectors, or the entire device.
AUTOMATIC PROGRAMMING ALGORITHM
MXIC's Automatic Programming algorithm requires the
user to only write program set-up commands (including
2 unlock write cycle and A0H) and a program command
(program data and address). The device automatically
mtimes the programming pulse width, provides the pro-
ogram verification, and counts the number of sequences.
.cThe device provides an unlock bypass mode with faster
programming. Only two write cycles are needed to pro-
Ugram a word or byte, instead of four. A status bit similar
t4to DATA polling and a status bit toggling between con-
esecutive read cycles, provide feedback to the user as
eto the status of the programming operation. Refer to write
hoperation status, table7, for more information on these
Sstatus bits.
www.DataP/N:PM0710
MXIC's Flash technology combines years of EPROM
experience to produce the highest levels of quality, reli-
ability, and cost effectiveness.The MX29LV400T/B elec-
trically erases all bits simultaneously using Fowler-
Nordheim tunneling. The bytes are programmed by us-
ing the EPROM programming mechanism of hot elec-
tron injection.
During a program cycle, the state-machine will control
the program sequences and command register will not
respond to any command set. During a Sector Erase
cycle, the command register will only respond to Erase
Suspend command. After Erase Suspend is completed,
the device stays in read mode. After the state machine
has completed its task, it will allow the command regis-
ter to respond to its full command set.
AUTOMATIC SELECT
The automatic select mode provides manufacturer and
device identification, and sector protection verification,
through identifier codes output on Q7~Q0.This mode is
mainly adapted for programming equipment on the de-
vice to be programmed with its programming algorithm.
When programming by high voltage method, automatic
select mode requires VID (11.5V to 12.5V) on address
pin A9 and other address pin A6, A1 as referring to Table
3. In addition, to access the automatic select codes in-
system, the host can issue the automatic select com-
REV. 1.4, NOV. 23, 2001
5
5 Page 
www.DataSheet4U.com
MX29LV400T/B
TABLE 6. EXPANDED SILICON ID CODE
Pins
Manufacture code
Device code
for MX29LV400T
Device code
www.DataSheet4U.cfoormMX29LV400B
Sector Protection
Verification
A0
Word VIL
Byte VIL
Word VIH
Byte VIH
Word VIH
Byte VIH
X
X
A1 Q15~Q8 Q7 Q6 Q5
VIL 00H
110
VIL X
110
VIL 22H
101
VIL X
101
VIL 22H
101
VIL X
101
VIH X
000
VIH X
000
Q4 Q3 Q2 Q1 Q0 Code(Hex)
0 0 0 1 0 00C2H
0 0 0 1 0 C2H
1 1 0 0 1 22B9H
1 1 0 0 1 B9H
1 1 0 1 0 22BAH
1 1 0 1 0 BAH
0 0 0 0 1 01H (Protected)
0 0 0 0 0 00H (Unprotected)
READING ARRAY DATA
RESET COMMAND
The device is automatically set to reading array data Writing the reset command to the device resets the
after device power-up. No commands are required to device to reading array data. Address bits are don't care
retrieve data.The device is also ready to read array data for this command.
after completing an Automatic Program or Automatic
Erase algorithm.
The reset command may be written between the se-
quence cycles in an erase command sequence before
After the device accepts an Erase Suspend command,
the device enters the Erase Suspend mode. The sys-
tem can read array data using the standard read tim-
erasing begins. This resets the device to reading array
data. Once erasure begins, however, the device ignores
reset commands until the operation is complete.
ings, except that if it reads at an address within erase-
suspended sectors, the device outputs status data. After
completing a programming operation in the Erase
Suspend mode, the system may once again read array
data with the same exception. See rase Suspend/Erase
Resume Commands” for more infor-mation on this mode.
The system must issue the reset command to re-en-
able the device for reading array data if Q5 goes high, or
The reset command may be written between the se-
quence cycles in a program command sequence be-fore
programming begins. This resets the device to reading
array data (also applies to programming in Erase
Suspend mode). Once programming begins,however, the
device ignores reset commands until the operation is
complete.
while in the autoselect mode. See the "Reset Command"
section, next.
www.DataSheet4U.comP/N:PM0710
The reset command may be written between the se-
quence cycles in an SILICON ID READ command
sequence. Once in the SILICON ID READ mode, the
reset command must be written to return to reading array
data (also applies to SILICON ID READ during Erase
Suspend).
If Q5 goes high during a program or erase operation,
writing the reset command returns the device to read-
ing array data (also applies during Erase Suspend).
REV. 1.4, NOV. 23, 2001
11
11 Page | ||
| Páginas | Total 59 Páginas | |
| PDF Descargar | [ Datasheet 29LV400BMC.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| 29LV400BMC | MX29LV400BMC | Macronix International |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |