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PDF GDPXA255 Data sheet ( Hoja de datos )
| Número de pieza | GDPXA255 | |
| Descripción | Processor | |
| Fabricantes | Intel | |
| Logotipo |  |
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Intel® PXA255 Processor
Electrical, Mechanical, and Thermal Specification
Product Features
Data Sheet
■ High Performance Processor
— Intel® XScale™ Microarchitecture
— 32 KB Instruction Cache
— 32 KB Data Cache
— 2 KB “mini” Data Cache
— Extensive Data Buffering
■ Intel® Media Processing Technology
— Enhanced 16-bit Multiply
— 40-bit Accumulator
■ Flexible Clocking
— CPU clock from 100 to 400 MHz
— Flexible memory clock ratios
— Frequency change modes
■ Rich Serial Peripheral Set
— AC97 Audio Port
— I2S Audio Port
— USB Client Controller
— High Speed UART
— Second UART with flow control
— UART with hardware flow control
— FIR and SIR infrared comm ports
■ Low Power
— Less than 500 mW Typical Internal
Dissipation
— Supply Voltage may be Reduced to
1.00 V
— Low Power/Sleep Modes
■ High Performance Memory Controller
— Four Banks of SDRAM - up to 100 MHz
— Five Static Chip Selects
— Support for PCMCIA or Compact Flash
— Companion Chip interface
■ Additional Peripherals for system
connectivity
— Multimedia Card Controller (MMC)
— SSP Controller
— Network SSP controller for baseband
— I2C Controller
— Two Pulse Width Modulators (PWMs)
— All peripheral pins double as GPIOs
■ Hardware debug features
■ Hardware Performance Monitoring features
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Order Number: 278805-002
1 page  
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PXA255 Processor — Electrical, Mechanical, and Thermal Specification
Revision History
Date
March 2003
February 2004
Revision
-001
-002
Description
First public release of the EMTS
Updated 400 MHz Idle mode power.
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Package Information
Table 3. Pin and Signal Descriptions for the PXA255 Processor (Sheet 3 of 9)
Pin Name
Type
Signal Descriptions
Reset State
L_DD[15]/
GPIO[73]
MBGNT/
GP[13]
ICOCZ
ICOCZ
LCD display data. (output) Transfers pixel information
from the LCD controller to the external LCD panel.
Memory controller grant. (output) Notifies an external
device that it has been granted the system bus.
Memory controller grant. (output) Notifies an external
device that it has been granted the system bus.
Pulled High -
Note[1]
Pulled High -
Note[1]
MBREQ/
GP[14]
Memory controller alternate bus master request.
ICOCZ (input) Allows an external device to request the system
bus from the memory controller.
Pulled High -
Note[1]
PCMCIA/CF Control Pins
nPOE/
GPIO[48]
ICOCZ
PCMCIA output enable. (output) Reads from PCMCIA
memory and to PCMCIA attribute space.
Pulled High -
Note[1]
nPWE/
GPIO[49]
PCMCIA write enable. (output) Performs writes to
ICOCZ PCMCIA memory and to PCMCIA attribute space. Also
used as the write enable signal for variable latency I/O.
Pulled High -
Note[1]
nPIOW/
GPIO[51]
ICOCZ
PCMCIA I/O write. (output) Performs write transactions
to PCMCIA I/O space.
Pulled High -
Note[1]
nPIOR/
GPIO[50]
ICOCZ
PCMCIA I/O read. (output) Performs read transactions
from PCMCIA I/O space.
Pulled High -
Note[1]
nPCE[2]/
GPIO[53]
ICOCZ
PCMCIA card enable 2. (output) Selects a PCMCIA
card. nPCE[2] enables the high byte lane and nPCE[1]
enables the low byte lane.
MMC clock. (output) Clock signal for the MMC controller.
Pulled High -
Note[1]
nPCE[1]/
GPIO[52]
PCMCIA card enable 1. (outputs) Selects a PCMCIA
ICOCZ card. nPCE[2] enables the high byte lane and nPCE[1]
enables the low byte lane.
Pulled High -
Note[1]
nIOIS16/
GPIO[57]
IO Select 16. (input) Acknowledge from the PCMCIA
ICOCZ card that the current address is a valid 16 bit wide I/O
address.
Pulled High -
Note[1]
nPWAIT/
GPIO[56]
ICOCZ
PCMCIA wait. (input) Driven low by the PCMCIA card to
extend the length of the transfers to/from the PXA255
processor processor.
Pulled High -
Note[1]
PCMCIA socket select. (output) Used by external
steering logic to route control, address, and data signals
PSKTSEL/
GPIO[54]
ICOCZ
to one of the two PCMCIA sockets. When PSKTSEL is
low, socket zero is selected. When PSKTSEL is high,
Pulled High -
Note[1]
socket one is selected. Has the same timing as the
mnPREG/
oGPIO[55]
ICOCZ
.cLCD Controller Pins
UL_DD(7:0)/
t4GPIO[65:58]
ICOCZ
eeL_DD[8]/
ShGPIO[66]
ICOCZ
address bus.
PCMCIA register select. (output) Indicates that the
target address on a memory transaction is attribute
space. Has the same timing as the address bus.
LCD display data. (outputs) Transfers pixel information
from the LCD Controller to the external LCD panel.
LCD display data. (output) Transfers pixel information
from the LCD controller to the external LCD panel.
Memory controller alternate bus master request.
(input) Allows an external device to request the system
bus from the Memory Controller.
Pulled High -
Note[1]
Pulled High -
Note[1]
Pulled High -
Note[1]
www.DataIntel® PXA255 Processor Electrical, Mechanical, and Thermal Specification
Sleep State
Note [3]
Note [3]
Note [3]
Note [5]
Note [5]
Note [5]
Note [5]
Note [5]
Note [5]
Note [5]
Note [5]
Note [5]
Note [5]
Note [3]
Note [3]
11
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet GDPXA255.PDF ] | |
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