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Número de pieza | EPM9480 | |
Descripción | Max 9000(a) Programmable Logic Device Family (6k Gates) | |
Fabricantes | Altera Corporation | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de EPM9480 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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December 2002, ver. 6.4
MAX 9000
Includes
® MAX 9000A Programmable Logic
Device Family
Data Sheet
Features...
■ High-performance CMOS EEPROM-based programmable logic
devices (PLDs) built on third-generation Multiple Array MatriX
(MAX®) architecture
■ 5.0-V in-system programmability (ISP) through built-in IEEE Std.
1149.1 Joint Test Action Group (JTAG) interface
■ Built-in JTAG boundary-scan test (BST) circuitry compliant with IEEE
Std. 1149.1-1990
■ High-density erasable programmable logic device (EPLD) family
ranging from 6,000 to 12,000 usable gates (see Table 1)
■ 10-ns pin-to-pin logic delays with counter frequencies of up to
144 MHz
■ Fully compliant with the peripheral component interconnect Special
Interest Group’s (PCI SIG) PCI Local Bus Specification, Revision 2.2
■ Dual-output macrocell for independent use of combinatorial and
registered logic
■ FastTrack® Interconnect for fast, predictable interconnect delays
■ Input/output registers with clear and clock enable on all I/O pins
■ Programmable output slew-rate control to reduce switching noise
■ MultiVolt™ I/O interface operation, allowing devices to interface
with 3.3-V and 5.0-V devices
■ Configurable expander product-term distribution allowing up to 32
product terms per macrocell
■ Programmable power-saving mode for more than 50% power
reduction in each macrocell
Table 1. MAX 9000 Device Features
Feature
EPM9320
EPM9320A
Usable gates
omFlipflops
.cMacrocells
Logic array blocks (LABs)
t4UMaximum user I/O pins
etPD1 (ns)
etFSU (ns)
htFCO (ns)
SfCNT (MHz)
ataAltera Corporation
www.DDS-M9000-6.4
6,000
484
320
20
168
10
3.0
4.5
144
EPM9400
8,000
580
400
25
159
15
5
7
118
EPM9480
10,000
676
480
30
175
10
3.0
4.8
144
EPM9560
EPM9560A
12,000
772
560
35
216
10
3.0
4.8
144
1
1 page www.DataSheet4U.com
MAX 9000 Programmable Logic Device Family Data Sheet
f
Functional
Description
The MAX 9000 family is supported by Altera’s MAX+PLUS II
development system, a single, integrated software package that offers
schematic, text—including VHDL, Verilog HDL, and the Altera
Hardware Description Language (AHDL)—and waveform design entry,
compilation and logic synthesis, simulation and timing analysis, and
device programming. The MAX+PLUS II software provides EDIF 2 0 0
and 3 0 0, LPM, and other interfaces for additional design entry and
simulation support from other industry-standard PC- and UNIX-
workstation-based EDA tools. The MAX+PLUS II software runs on
Windows-based PCs as well as Sun SPARCstation, HP 9000 Series
700/800, and IBM RISC System/6000 workstations.
For more information on development tools, see the MAX+PLUS II
Programmable Logic Development System & Software Data Sheet.
MAX 9000 devices use a third-generation MAX architecture that yields
both high performance and a high degree of utilization for most
applications. The MAX 9000 architecture includes the following elements:
■ Logic array blocks
■ Macrocells
■ Expander product terms (shareable and parallel)
■ FastTrack Interconnect
■ Dedicated inputs
■ I/O cells
Figure 1 shows a block diagram of the MAX 9000 architecture.
wwAwlter.aDCoarpotraatiSonheet4U.com
5
5 Page www.DataSheet4U.com
MAX 9000 Programmable Logic Device Family Data Sheet
Parallel Expanders
Parallel expanders are unused product terms that can be allocated to a
neighboring macrocell to implement fast, complex logic functions.
Parallel expanders allow up to 20 product terms to directly feed the
macrocell OR logic, with five product terms provided by the macrocell and
15 parallel expanders provided by neighboring macrocells in the LAB.
Figure 5 shows how parallel expanders can feed the neighboring
macrocell.
Figure 5. MAX 9000 Parallel Expanders
Unused product terms in a macrocell can be allocated to a neighboring macrocell.
33 Row
FastTrack
Interconnect
Signals
LAB Local
Array
From
Previous
Macrocell
Product-
Term
Select
Matrix
Preset
Clock
Clear
Macrocell
Product-
Term Logic
.com16 Local 16 Shared
Feedbacks Expanders
www.DataSheet4UAltera Corporation
Product-
Term
Select
Matrix
Preset
Clock
Clear
Macrocell
Product-
Term Logic
To Next
Macrocell
11
11 Page |
Páginas | Total 30 Páginas | |
PDF Descargar | [ Datasheet EPM9480.PDF ] |
Número de pieza | Descripción | Fabricantes |
EPM9480 | Max 9000(a) Programmable Logic Device Family (6k Gates) | Altera Corporation |
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