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PDF SC3048B Data sheet ( Hoja de datos )

Número de pieza SC3048B
Descripción 444.0 MHz Differential Sine-Wave Clock
Fabricantes RF Monolithics 
Logotipo RF Monolithics Logotipo



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• Quartz SAW Frequency Stability
• Fundamental Fixed Frequency
• Excellent Jitter and Symmetry
• Rugged, Miniature, Surface-Mount Case
• Low-Voltage Power Supply (3.3 VDC)
This digital clock is designed for use in critical timing applications. Fundamental-mode oscillation is made pos-
sible by surface-acoustic-wave (SAW) technology. The design results in low jitter, compact size, and low pow-
er consumption. Differential outputs provide a sine wave that is made to drive 50 loads.
SC3048B
444.0 MHz
Differential
Sine-Wave
Clock
Absolute Maximum Rating
Power Supply Voltage (VCC at Terminal 1)
Input Voltage (ENABLE at Terminal 8)
Case Temperature (Powered or Storage)
Value
0 to +4.0
0 to +4.0
-40 to +85
Units
VDC
VDC
°C
SMC-8 Case
Electrical Characteristics
Output Frequency
Q and Q Output
Characteristic
Absolute Frequency
Tolerance from 444.000 MHz
Voltage into 50(VSWR 1.2)
Operating Load VSWR
Sym
fO
fO
VO
Notes
1, 2
1, 3
Minimum
443.911
0.5
Typical
Maximum
444.089
±200
4.5
2:1
Units
MHz
ppm
dBm
Symmetry
3, 4, 5
49
51 %
Harmonic Spurious
Nonharmonic Spurious
3, 4, 6
-30 dBc
-60 dBc
Q and Q Period Jitter
No Noise on VCC
3, 4, 6, 7
15 30 psP-P
200 mVP-P from 1 MHz to ½ fO on
3, 4, 7, 8
35 psP-P
Output (Disabled)
Amplitude into 50
3, 9
75 mVP-P
Output DC Resistance (between Q & Q)
3 100
K
ENABLE (Terminal 14)
Input HIGH Voltage
VIH
VCC-0.1
VCC
VCC+0.1
V
Input LOW Voltage VIL 0.0
0.20 V
Input HIGH Current
IIH 3, 9
3 5 mA
Input LOW Current
IIL
-1 mA
Propagation Delay
tPD
1 ms
DC Power Supply
Operating Voltage
Operating Current
VCC
ICC
1, 3
+3.13
+3.30
18
+3.47
40
VDC
mA
Operating Ambient Temperature
TA 1, 3
0
+70 °C
Lid Symbolization (YY = Year, WW = Week)
RFM SC3048B 444.00 MHz YYWW
mCAUTION: Electrostatic Sensitive Device. Observe precautions for handling.
oNOTES:
.c1. Unless otherwise noted, all specifications include any combination of load 6. Jitter and other spurious outputs induced by externally generated electrical noise
UVSWR, VCC, and TA. In addition, Q and Q are terminated into 50 loads to
ground. (See: Typical Test Circuit.)
on VCC or mechanical vibration are not included. Dedicated external voltage
regulation and careful PCB layout are recommended for optimum performance.
t42. One or more of the following United States patents apply: 4,616,197; 4,670,681; 7. Applies to period jitter of Q and Q. Measurements are made with the Tektronix
e4,760,352.
CSA803 signal analyzer with at least 1000 samples.
e3. The design, manufacturing process, and specifications of this device are subject 8. Period jitter measured with a 200 mVP-P sine wave swept from 1 MHz to one-half
h4.
taS5.
to change without notice.
Only under the nominal conditions of 50 load impedance with VSWR 1.2 and
nominal power supply voltage.
Symmetry is defined as the pulse width (in percent of total period) measured at
the 50% points of Q or Q. (See: Timing Definitions.)
9.
of fO at the VCC power supply terminal.
The outputs are enabled when Terminal 8 is at logic HIGH. Propagation delay is
defined as the time from the 50% point on the rising edge of ENABLE to the 90%
point on the rising edge of the output amplitude or as the fall time from the 50%
point to the 10% point. (SEE: Timing Definitions.)
.DaRF Monolithics, Inc. Phone: (972) 233-2903
Fax: (972) 387-9148
RFM Europe
Phone: 44 1963 251383
Fax: 44 1963 251510
www©1999 by RF Monolithics, Inc. The stylized RFM logo are registered trademarks of RF Monolithics, Inc.
http://www.rfm.com
SC3048B-113000
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