PDF ICS527-04 Data sheet ( Hoja de datos )

Número de pieza	ICS527-04
Descripción	Clock Slicer User Configurable PECL input Zero Delay Buffer
Fabricantes	Integrated Circuit Systems
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No Preview Available ! www.DataSheet4U.com ICS527-04 Clock Slicer User Configurable PECL input Zero Delay Buffer Description The ICS527-04 Clock Slicer is the most flexible way to generate an output clock from an input clock with zero skew. The user can easily configure the device to produce nearly any output clock that is multiplied or divided from the input clock. The part supports non-integer multiplications and divisions. Using Phase-Locked Loop (PLL) techniques, the device accepts an input clock up to 200 MHz and produces an output clock up to 160 MHz. The ICS527-04 aligns rising edges on PECLIN with FBPECL at a ratio determined by the reference and feedback dividers. For other PECL output clocks, see the ICS507-01, ICS525-03, or the MK3707. For PECL in and CMOS out, see the ICS527-02. For CMOS in and PECL out with zero delay, use the ICS527-03. Features • Packaged as 28-pin SSOP (150 mil body) • Synchronizes fractional clocks rising edges • CMOS in to PECL out • PECL in to PECL out • Pin selectable dividers • Zero input to output skew • User determines the output frequency - no software needed • Slices frequency or period • Input clock frequency of 1.5 MHz - 200 MHz • Output clock frequencies up to 160 MHz • Very low jitter • Duty cycle of 45/55 • Operating voltage of 3.3 V • Advanced, low power CMOS process Block Diagram PECLIN PECLIN Divide by 2 1 0 R6:R0 7 Reference Divider FBPECL FBPECL Divide by 2 1 0 Feedback Divider IRANGE 7 F6:F0 2 VDD 560 ohm RES VDD Phase Comparator, Charge Pump, and Loop Filter VCO Output Divider 2 GND 2 S1:S0 VDD 68 ohm PECLO 180 ohm VDD 68 ohm 180 ohm PECLO www.DataSheet4U.com MDS 527-04 D 1 Revision 122804 Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com 1 page www.DataSheet4U.com ICS527-04 Clock Slicer User Configurable PECL input Zero Delay Buffer Multiple Output Example In this example, an input clock of 125 MHz is used. Four low skew copies of 50 MHz PECL are required aligned to the 125 MHz input clock. The following solution uses the ICS554-01A, which is a 1 to 4 PECL buffer with low pin to pin skew. VDD 0.01 F 50 MHz 125 MHz 125 MHz R5 R6 IRANGE S0 S1 VDD FBPECL FBPECL GND PECLIN PECLIN F0 F1 F2 R4 R3 R2 R1 R0 VDD PECLO PECLO GND RES F6 F5 F4 F3 0.01 F RN RN 560 OE VDD RN Q0 RN 0.01 F RN Q0 Q1 RN Q1 GND IN NC VDD Q3 RN Q3 RN 0.01 F Q2 RN Q2 RN GND IN The layout design above produces the waveforms shown below. 125 MHz, PECLIN 50 MHz, PECLO (Complementary outputs are not shown) Using the equation for selecting dividers gives: (FDW + 2) 50 MHz = 125 MHz * (RDW + 2) If FDW = 0, then RDW = 3. This gives the required divide-by-5 function. Setting pin IRANGE = 1 (by leaving it unconnected and using the internal pull-up) allows a higher speed input clock like the 125 MHz. The FBPECL pair pins are connected to the Q1 outputs (chosen arbitrarily) of the ICS554. This aligns all the outputs of the ICS554 with the 125 MHz input since the ICS527-04 aligns rising edges on the PECLIN and FBPECL pins. In this example, the resistor network needed for each PECLO output is represented by the RN boxes. www.DataSheet4U.com MDS 527-04 D 5 Revision 122804 Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com 5 Page

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Número de pieza	Descripción	Fabricantes
ICS527-01	User Configurable Zero Delay Buffer	Integrated Circuit Systems
ICS527-02	Clock Slicer User Configurable PECL Input Zero Delay Buffer	Integrated Circuit Systems
ICS527-03	Clock Slicer User Configurable PECL Output Zero Delay Buffer	Integrated Circuit Systems
ICS527-04	Clock Slicer User Configurable PECL input Zero Delay Buffer	Integrated Circuit Systems

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