|
|
PDF ICS527-03 Data sheet ( Hoja de datos )
| Número de pieza | ICS527-03 | |
| Descripción | Clock Slicer User Configurable PECL Output Zero Delay Buffer | |
| Fabricantes | Integrated Circuit Systems | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de ICS527-03 (archivo pdf) en la parte inferior de esta página. Total 8 Páginas | ||
|
No Preview Available !
www.DataSheet4U.com
Preliminary Information
ICS527-03
Clock Slicer User Configurable PECL Output Zero Delay Buffer
Description
The ICS527-03 is the most flexible way to generate an
output clock from an input clock with zero skew. The
user can easily configure the device to produce nearly
any output clock that is multiplied or divided from the
input clock. The part supports non-integer
multiplications and divisions. Using Phase-Locked
Loop (PLL) techniques, the device accepts an input
clock up to 200 MHz and produces an output clock up
to 160 MHz.
The ICS527-03 aligns rising edges on CLKIN with
FBPECL at a ratio determined by the reference and
feedback dividers.
For a PECL input and output clock with zero delay, use
the ICS527-04.
Features
• Packaged as 28 pin SSOP (150 mil body)
• Synchronizes fractional clocks rising edges
• CMOS in to PECL out
• Pin selectable dividers
• Zero input to output skew
• User determines the output frequency - no software
needed
• Slices frequency or period
• Input clock frequency of 1.5 MHz to 200 MHz
• Output clock frequencies from 2.5 MHz to 160 MHz
• Very low jitter
• Duty cycle of 45/55
• Operating voltage of 3.3 V
• Advanced, low power CMOS process
Block Diagram
CLKIN
Divide
by 2
R6:R0
7
1 Reference
0 Divider
FBPECL
FBPECL
Divide
by 2
1 Feedback
0 Divider
DIV2
7
F6:F0
2 VDD
Phase Comparator,
Charge Pump, and
Loop Filter
VCO
Output
Divider
2 GND
PDTS
2
S1:S0
VDD
68 ohm
PECL
180 ohm
VDD
68 ohm
PECL
180 ohm
www.DataSheet4U.com
MDS 527-03 B
1
Revision 122804
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
1 page  
www.DataSheet4U.com
Preliminary Information
ICS527-03
Clock Slicer User Configurable PECL Output Zero Delay Buffer
Multiple Output Example
In this example, an output clock of 125 MHz is used. Four copies of 50 MHz are required, de-skewed and
aligned to the 125 MHz input clock. The following solution uses the ICS554-01A which has buffers with low
pin to pin skew. The layout diagram below will produce the waveforms shown on the bottom.
PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
1) Each 0.01µF decoupling capacitor should be
mounted on the component side of the board as close
to the VDD pin as possible. No via’s should be used
between decoupling capacitor and VDD pin. The PCB
trace to VDD pin should be kept as short as possible,
as should the PCB trace to the ground via.
www.DataSheet4U.com
2) PECL termination networks should be located as
close to the outputs as possible.
3) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers. Other signal traces should be routed
away from the ICS527-03. This includes signal traces
just underneath the device, or on layers adjacent to the
ground plane layer used by the device.
MDS 527-03 B
5
Revision 122804
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet ICS527-03.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| ICS527-01 | User Configurable Zero Delay Buffer | Integrated Circuit Systems |
| ICS527-02 | Clock Slicer User Configurable PECL Input Zero Delay Buffer | Integrated Circuit Systems |
| ICS527-03 | Clock Slicer User Configurable PECL Output Zero Delay Buffer | Integrated Circuit Systems |
| ICS527-04 | Clock Slicer User Configurable PECL input Zero Delay Buffer | Integrated Circuit Systems |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |