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PDF ICS525-11 Data sheet ( Hoja de datos )

Número de pieza ICS525-11
Descripción (ICS525-11/12) User Configurable Clock
Fabricantes Integrated Circuit Systems 
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ICS525-01/02/11/12
User Configurable Clock
Description
The ICS525-01/02/11/12 are the most flexible way to
generate a high-quality, high-accuracy, high-frequency
clock output from an inexpensive crystal or clock input.
The user can configure the device to produce nearly
any output frequency from any input frequency by
grounding or floating the select pins. Neither
microcontroller, software, nor device programmer are
needed to set the frequency. Using Phase-Locked
Loop (PLL) techniques, the device accepts a standard
fundamental mode, inexpensive crystal to produce
output clocks up to 250 MHz. It can also produce a
highly accurate output clock from a given input clock,
keeping them frequency locked together.
For similar capability with a serial interface, use the
ICS307. For simple multipliers to produce common
frequencies, refer to the ICS50x family of parts, which
are smaller and more cost effective.
These products are intended for clock generation. They
have low output jitter (variation in the output period), but
input to output skew and jitter are not defined nor
guaranteed. For applications which require defined
input to output timing, use the ICS527-01.
Features
Packaged as 28-pin SSOP (150 mil body)
Industrial and commercial versions available in Pb
(lead) free package
User determines the output frequency by setting all
internal dividers
Eliminates need for custom oscillators
No software needed
Online calculator determines register settings
Pull-ups on all select inputs
Input crystal frequency of 5 - 27 MHz
Input clock frequency of 2 - 50 MHz
Very low jitter
Duty cycle of 45/55 up to 200 MHz
Operating voltage of 3.0 V or 5.5 V
Ideal for oscillator replacement
Industrial temperature version available
For Zero Delay, refer to the ICS527
Block Diagram
PD
X1/ICLK
Crystal or clock
input X2
Optional crystal capacitors
Crystal
Oscillator
Reference
Divider
7
R6:R0
2 VDD
Phase Comparator,
Charge Pump, and
Loop Filter
VCO
Divider
VCO
9 2 GND
V8:V0
Output
Divider
3
S2:S0
CLK
REF
MDS 525-01/02/11/12 Q
1
Revision 101105
Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com

1 page




ICS525-11 pdf
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External Components/Crystal
Selection
Decoupling Capacitors
The ICS525-01/02/11/12 requries two 0.01µF
decoupling capacitors to be connected between VDD
and GND, one on each side of the chip. The capacitor
must be connected close to the device to minimize lead
inductance.
External Resistors
A 33series termination resistor should be used on
the CLK and REF pins.
Crystal Load Capacitors
The approximate total on-chip capacitance for a crystal
is 16 pF, so a parallel resonant, fundamental mode
crystal with this value of load (correlation) capacitance
should be used. For crystals with a specified load
capacitance greater than 16 pF, crystal capacitors may
be connected from each of the pins X1 and X2 to
Ground as shown in the block diagram. The value (in
pF) of these crystal caps should be (CL -16)*2, where
CL is the crystal load capacitance in pF. These external
capacitors are only required for applications where the
exact frequency is critical. For a clock input, connect to
X1 and leave X2 unconnected (no capacitors on
either).
Determining the Output Frequency
Users have full control in setting the desired output
frequency over the range shown in the tables on pages
3-4. To replace a standard oscillator, users should
connect the divider select input pins directly to ground
(or VDD, although this is not required because of
internal pull-ups) during Printed Circuit Board layout.
The ICS525 will automatically produce the correct
frequency when all components are soldered. It is also
possible to connect the inputs to parallel I/O ports to
switch frequencies. By choosing divides carefully, the
number of inputs which need to be changed can be
minimized. Observe the restrictions on allowed values
of VDW and RDW.
Configuration Pin Settings
The output of the ICS525 can be determined by the
following simple equation:
ICS525-01/02/11/12
User Configurable Clock
CLK Frequency = Input Frequency × 2x(---R-----(D---V-W---D-----+W-----2--+-)----8----)O-----D---
Where:
Reference Divider Word (RDW) = 0 to 127 (0 not
permitted for ICS525-01/-11)
VCO Divider Word (VDW) = 0 to 511 (0, 1, 2, 3 not
permitted for ICS525-01/-11)
Output Divider (OD) = values on pages 3-4
Also, the following operating ranges should be
observed:
1. The output frequency must be in the ranges listed on
pages 3-4.
2. The phase detector frequency must be above 200
kHz.
200kHz < -I--n---p---(-u--R--t--F-D---r-W--e----q--+-u----2e---)-n----c---y--
Since all of the inputs have pull-up resistors, it is only
necessary to ground the pins that need to be set to
zero.
Which Part to Use?
The ICS525-01 is the original configurable clock.
The ICS525-02 has a higher maximum output
grequency and a slightly different set of output dividers.
The ICS525-11 has the same divider set as the -01 but
is optimized for low frequency operation.
The ICS525-12 has the same divider set as the -02 but
is optimized for low frequency operation.
To determine the best combination of VCO, reference,
and output divide, use the ICS525 Calculator on our
web site.
MDS 525-01/02/11/12 Q
5
Revision 101105
Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com

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