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PDF EP20K600Exxxx Data sheet ( Hoja de datos )
| Número de pieza | EP20K600Exxxx | |
| Descripción | (EP20KxxxE) Programmable Logic Device Family | |
| Fabricantes | Altera Corporation | |
| Logotipo |  |
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February 2002, ver. 4.3
®
APEX 20K
Programmable Logic
Device Family
Data Sheet
Features...
■ Industry’s first programmable logic device (PLD) incorporating
system-on-a-programmable-chip (SOPC) integration
– MultiCoreTM architecture integrating look-up table (LUT) logic,
product-term logic, and embedded memory
– LUT logic used for register-intensive functions
– Embedded system block (ESB) used to implement memory
functions, including first-in first-out (FIFO) buffers, dual-port
RAM, and content-addressable memory (CAM)
– ESB implementation of product-term logic used for
combinatorial-intensive functions
■ High density
– 30,000 to 1.5 million typical gates (see Tables 1 and 2)
– Up to 51,840 logic elements (LEs)
– Up to 442,368 RAM bits that can be used without reducing
available logic
– Up to 3,456 product-term-based macrocells
Table 1. APEX 20K Device Features Note (1)
Feature EP20K30E EP20K60E
Maximum
system
gates
Typical
gates
LEs
ESBs
113,000
30,000
1,200
12
162,000
60,000
2,560
16
Maximum
RAM bits
24,576
32,768
Maximum
macrocells
Maximum
user I/O
pins
192
128
256
196
EP20K100
263,000
100,000
4,160
26
53,248
416
252
EP20K100E EP20K160E EP20K200
263,000
404,000
526,000
100,000
4,160
26
53,248
416
246
160,000
6,400
40
81,920
640
316
200,000
8,320
52
106,496
832
382
EP20K200E
526,000
200,000
8,320
52
106,496
832
376
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Altera Corporation
DS-APEX20K-4.3
1
1 page  
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APEX 20K Programmable Logic Device Family Data Sheet
Table 5. APEX 20K FineLine BGA Package Options & I/O Count Notes (1), (2)
Device
144 Pin
324 Pin
484 Pin
672 Pin
1,020 Pin
EP20K30E
93 128
EP20K60E
93 196
EP20K100
252
EP20K100E
93
246
EP20K160E
316
EP20K200
382
EP20K200E
376 376
EP20K300E
408
EP20K400
502 (3)
EP20K400E
488 (3)
EP20K600E
508 (3)
588
EP20K1000E
508 (3)
708
EP20K1500E
808
Notes to tables:
(1) I/O counts include dedicated input and clock pins.
(2) APEX 20K device package types include thin quad flat pack (TQFP), plastic quad flat pack (PQFP), power quad flat
pack (RQFP), 1.27-mm pitch ball-grid array (BGA), 1.00-mm pitch FineLine BGA, and pin-grid array (PGA)
packages.
(3) This device uses a thermally enhanced package, which is taller than the regular package. Consult the Altera Device
Package Information Data Sheet for detailed package size information.
Table 6. APEX 20K QFP, BGA & PGA Package Sizes
Feature
Pitch (mm)
Area (mm2)
Length × Width
(mm × mm)
144-Pin TQFP 208-Pin QFP 240-Pin QFP 356-Pin BGA 652-Pin BGA 655-Pin PGA
0.50
484
22 × 22
0.50
924
30.4 × 30.4
0.50
1,218
34.9 × 34.9
1.27
1,225
35 × 35
1.27
2,025
45 × 45
–
3,906
62.5 × 62.5
Table 7. APEX 20K FineLine BGA Package Sizes
Feature
Pitch (mm)
Area (mm2)
Length × Width (mm × mm)
144 Pin
1.00
169
13 × 13
324 Pin
1.00
361
19 × 19
484 Pin
1.00
529
23 × 23
672 Pin
1.00
729
27 × 27
1,020 Pin
1.00
1,089
33 × 33
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Altera Corporation
5
5 Page 
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APEX 20K Programmable Logic Device Family Data Sheet
Logic Array Block
Each LAB consists of 10 LEs, the LEs’ associated carry and cascade chains,
LAB control signals, and the local interconnect. The local interconnect
transfers signals between LEs in the same or adjacent LABs, IOEs, or ESBs.
The Quartus II Compiler places associated logic within an LAB or adjacent
LABs, allowing the use of a fast local interconnect for high performance.
Figure 3 shows the APEX 20K LAB.
APEX 20K devices use an interleaved LAB structure. This structure allows
each LE to drive two local interconnect areas. This feature minimizes use
of the MegaLAB and FastTrack interconnect, providing higher
performance and flexibility. Each LE can drive 29 other LEs through the
fast local interconnect.
Figure 3. LAB Structure
Row
Interconnect
MegaLAB Interconnect
LEs drive local
MegaLAB, row,
and column
interconnects.
To/From
Adjacent LAB,
ESB, or IOEs
Local Interconnect
The 10 LEs in the LAB are driven by
two local interconnect areas. These LEs
can drive two local interconnect areas.
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Altera Corporation
To/From
Adjacent LAB,
ESB, or IOEs
Column
Interconnect
11
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