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PDF ICS94236 Data sheet ( Hoja de datos )
| Número de pieza | ICS94236 | |
| Descripción | Programmable System Clock Chip | |
| Fabricantes | Integrated Circuit System | |
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Integrated
Circuit
Systems, Inc.
ICS94236
Programmable System Clock Chip for AMD - K7™ processor
Recommended Application:
VIA KX/KT133 style chipset
Output Features:
• 1 - Differential pair open drain CPU clocks
• 1 - CPU clock @ 3.3V
• 13 - SDRAM @ 3.3V
• 6 - PCI @3.3V,
• 1 - 48MHz, @3.3V fixed.
• 1 - 24/48MHz @ 3.3V
• 2 - REF @3.3V, 14.318MHz.
Features:
• Programmable ouput frequency.
• Programmable ouput rise/fall time.
• Programmable PCI_F and PCICLK skew.
• Spread spectrum for EMI control typically
by 7dB to 8dB,
with programmable spread percentage.
• Watchdog timer technology to reset system
if over-clocking causes malfunction.
• Uses external 14.318MHz crystal.
• FS pins for frequency select
Pin Configuration
VDDREF
REF0
GND
X1
X2
VDDPCI
1FS4/PCICLK_F
**FS3/PCICLK0
GND
*SEL24_48#/PCICLK1
PCICLK2
PCICLK3
PCICLK4
VDDPCI
BUFFER IN
GND
SDRAM11
SDRAM10
VDDSDR
SDRAM9
SDRAM8
GND
SDATA
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 REF1/FS2**
47 GND
46 CPUCLK
45 GND
44 CPUCLKC0
43 CPUCLKT0
42 VDDCPU
41 PD#*
40 SDRAM_OUT
39 GND
38 SDRAM0
37 SDRAM1
36 VDDSDR
35 SDRAM2
34 SDRAM3
33 GND
32 SDRAM4
31 SDRAM5
30 VDDSDR
29 SDRAM6
28 SDRAM7
27 VDD48
26 48MHz/FS0*
25 24/48MHz/FS1**
48-Pin 300mil SSOP
* Internal Pull-up Resistor of 120K to VDD.
** Internal Pull-down Resistor of 120K to GND.
1 Internal Pull-down Resistor of 60K to GND.
Block Diagram
PLL2
X1 XTAL
X2 OSC
PLL1
Spread
Spectrum
/2
CPU
DIVDER
SEL24_48#
SDATA
SCLK
FS (4:0)
PD#
Control
Logic
Config.
Reg.
PCI
DIVDER
SDRAM
DRIVER
BUFFER IN
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0451A—01/10/03
48MHz
24_48MHz
REF (1:0)
CPUCLK
CPUCLKC0
CPUCLKT0
PCICLK (4:0)
PCICLK_F
SDRAM (11:0)
SDRAM_OUT
Functionality
FS3 FS2 FS1 FS0
0000
000 1
00 10
00 11
0 100
0 10 1
0 110
0 111
10 0 0
100 1
10
10
10 11
1 10 0
110 1
1 1 10
1111
CPU
(MHz)
95.00
100.00
102.00
105.00
110.00
113.00
115.00
120.00
133.33
135.00
137.00
139.00
141.00
143.00
145.00
150.00
PCICLK
(MHz)
31.67
33.33
34.00
35.00
36.67
37.67
38.33
40.00
33.33
33.75
34.25
34.75
35.25
35.75
36.25
37.50
* 16 additional frequency selectables via FS4, refer to page5
for frequency table.
1 page  
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ICS94236
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
Bit
Description
PWD
Bit2 Bit7 Bit6 Bit5 Bit4 CPUCLK PCICLK
FS4 FS3 FS2 FS1 FS0 MHz
MHz
Spread %
0 0 0 0 0 95.00
31.67
0.45% Center Spread
0 0 0 0 1 100.00 33.33
0.45% Center Spread
0 0 0 1 0 102.00 34.00
0.45% Center Spread
0 0 0 1 1 105.00 35.00
0.45% Center Spread
0 0 1 0 0 110.00 36.67
0.45% Center Spread
0 0 1 0 1 113.00 37.67
0.45% Center Spread
0 0 1 1 0 115.00 38.33
0.45% Center Spread
0 0 1 1 1 120.00 40.00
0.45% Center Spread
0 1 0 0 0 133.33 33.33
0.45% Center Spread
0 1 0 0 1 135.00 33.75
0.45% Center Spread
0 1 0 1 0 137.00 34.25
0.45% Center Spread
0 1 0 1 1 139.00 34.75
0.45% Center Spread
0 1 1 0 0 141.00 35.25
0.45% Center Spread
0 1 1 0 1 143.00 35.75
0.45% Center Spread
Bit 0 1 1 1 0
(2,7:4) 0 1 1 1 1
145.00
150.00
36.25
37.50
0.45% Center Spread
0.45% Center Spread Note 1
1 0 0 0 0 100.90 33.63
0.45% Center Spread
1 0 0 0 1 100.00 33.33
0 to - 0.7% spread
1 0 0 1 0 103.00 34.33
0.45% Center Spread
1 0 0 1 1 107.00 35.67
0.45% Center Spread
1 0 1 0 0 117.00 39.00
0.45% Center Spread
1 0 1 0 1 120.00 30.00
0.45% Center Spread
1 0 1 1 0 123.00 30.75
0.45% Center Spread
1 0 1 1 1 125.00 31.25
0.45% Center Spread
1 1 0 0 0 133.33 33.33
0 to - 0.7% spread
1 1 0 0 1 133.90 33.48
0.45% Center Spread
1 1 0 1 0 147.00 36.75
0.45% Center Spread
1 1 0 1 1 151.00 37.75
0.45% Center Spread
1 1 1 0 0 153.00 38.25
0.45% Center Spread
1 1 1 0 1 155.00 38.75
0.45% Center Spread
1 1 1 1 0 160.00 40.00
0.45% Center Spread
1 1 1 1 1 200.00 50.00
0.45% Center Spread
Bit 3
0-Frequency is selected by hardware select, latched inputs
1- Frequency is selected by Bit 2,7:4
0
Bit 1
0- Normal
1- Spread spectrum enable
1
Bit 0
0- Running
1- Tristate all outputs
0
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Note: Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
0451A—01/10/03
5
5 Page 
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ICS94236
Electrical Characteristics - REF(0:1)
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
Output High Voltage
VOH5
IOH = -12 mA
Output Low Voltage
VOL5
IOL = 9 mA
Output High Current
IOH5
VOH = 2.0 V
Output Low Current
IOL5
VOL = 0.8 V
Rise Time1
tr5 VOL = 0.4 V, VOH = 2.4 V
Fall Time1
tf5 VOH = 2.4 V, VOL = 0.4 V
Duty Cycle1
dt5
VT = 1.5V
Jitter, Cycle-to-cycle1
tjcyc-cyc2B
VT = 1.5V
1Guaranteed by design, not 100% tested in production.
MIN TYP MAX UNITS
2.4 V
0.4 V
-22 mA
16 mA
1.2 4
ns
1.5 4
ns
45 54.1 55
%
1007 1100
ps
Electrical Characteristics - CPUCLK (Open Drain)
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Output Impedance
Output High Voltage
Output Low Voltage
Output Low Current
Rise Time1
Fall Time1
Differential voltage-AC1
Differential voltage-DC1
Z0
VOH2B
VOL2B
IOL2B
tr2B
tf2B
VDIF
VDIF
VO = VX
Termination to Vpull-up(external)
Termination to Vpull-up(external)
VOL = 0.3 V
VOL = 0.3 V, VOH = 1.2 V
VOH = 1.2 V, VOL = 0.3 V
Note 2
Note 2
1
18
0.4
Vpu
+0.6
0.2
Vpu
+0.6
1.2
0.4
0.9
0.9
V
V
mA
ns
ns
V
V
Differential Crossover
VX
Note 3
Duty Cycle1
dt2B
VT = 50%
Skew1
tsk2B
VT = 50%
Jitter, Cycle-to-cycle1
tjcyc-cyc2B
VT = VX
Jitter, Absolute1
tjabs2B
VT = 50%
1 - Guaranteed by design, not 100% tested in production.
550 1100
45 51
55
163 200
201 250
-250
250
mV
%
ps
ps
ps
2 - VDIF specifies the minimum input differential voltage (VTR-VCP) required for switching, where VTR is the "true"
input level and VCP is the "complement" input level
3 - Vpullup(external)=1.5V, Min=Vpullup(External)/2-150mV, Max=Vpullup(external)/2+150mV
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0451A—01/10/03
11
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet ICS94236.PDF ] | |
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