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PDF ICS94215 Data sheet ( Hoja de datos )

Número de pieza ICS94215
Descripción Programmable System Clock Chip
Fabricantes Integrated Circuit Systems 
Logotipo Integrated Circuit Systems Logotipo



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Integrated
Circuit
Systems, Inc.
ICS94215
Programmable System Clock Chip for AMD - K7™ Processor
Recommended Application:
VIA KX/KT133 style chipset
Output Features:
• 1 - Differential pair open drain CPU clocks
• 1 - CPU clock @ 3.3V
• 13 - SDRAM @ 3.3V
• 6 - PCI @3.3V,
• 1 - 48MHz, @3.3V fixed.
• 1 - 24/48MHz @ 3.3V
• 2 - REF @3.3V, 14.318MHz.
Features:
• Programmable ouput frequency.
• Programmable ouput rise/fall time.
• Programmable PCI_F and PCICLK skew.
• Spread spectrum for EMI control typically
by 7dB to 8dB,
with programmable spread percentage.
• Watchdog timer technology to reset system
if over-clocking causes malfunction.
• Uses external 14.318MHz crystal.
• FS pins for frequency select
Pin Configuration
VDD1
REF0/CPU_STOP#*
GND
X1
X2
VDD2
*MODE/PCICLK_F
*FS3/PCICLK0
GND
*SEL24_48#/PCICLK1
PCICLK2
PCICLK3
PCICLK4
VDD2
BUFFER IN
GND
SDRAM11
SDRAM10
VDD3
SDRAM9
SDRAM8
GND
SDATA
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 REF1/FS2*
47 GND
46 CPUCLK
45 GND
44 CPUCLKC0
43 CPUCLKT0
42 VDDCPU
41 PD#*
40 SDRAM_OUT
39 GND
38 SDRAM0
37 SDRAM1
36 VDD3
35 SDRAM2
34 SDRAM3
33 GND
32 SDRAM4
31 SDRAM5
30 VDD3
29 SDRAM6
28 SDRAM7
27 VDD4
26 48MHz/FS0*
25 24/48MHz/FS1*
48-Pin 300mil SSOP
* Internal Pull-up Resistor of 120K to VDD
Block Diagram
PLL2
X1 XTAL
X2 OSC
PLL1
Spread
Spectrum
/2
CPU
DIVDER
Stop
SEL24_48#
SDATA
SCLK
Control
Logic
PCI
DIVDER
FS (3:0)
PD#
Config.
Reg.
SDRAM
DRIVER
CPU_STOP#
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BUFFER IN
0442C—07/03/02
48MHz
24_48MHz
REF (1:0)
CPUCLK
CPUCLKC0
CPUCLKT0
PCICLK (4:0)
PCICLK_F
SDRAM (11:0)
SDRAM_OUT
Functionality
FS3 FS2 FS1 FS0
0000
000 1
00 10
00 11
0 100
0 10 1
0 110
0 111
10 0 0
100 1
10
10
10 11
1 10 0
110 1
1 1 10
1111
CPU
(MHz)
90.00
95.00
101.00
102.00
100.90
103.00
105.00
100.00
107.00
109.00
110.00
111.00
113.00
115.00
117.00
133.30
PCICLK
(MHz)
30.00
31.67
33.67
34.00
33.57
34.33
35.00
33.33
35.67
36.33
36.67
37.00
37.67
38.33
39.00
33.33

1 page




ICS94215 pdf
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ICS94215
Brief I2C registers description for ICS94215
Programmable System Frequency Generator
Register Name
Functionality &
Frequency Select
Register
Output Control
Registers
Byte
0
1-6
Vendor ID & Revision
ID Registers
7
Byte Count
Read Back Register
Watchdog Timer
Count Register
8
9
Description
Output frequency, hardware / I2C
frequency select, spread spectrum &
output enable control register.
Active / inactive output control
registers/latch inputs read back.
Byte 11 bit[7:4] is ICS vendor id -
1001. Other bits in this register
designate device revision ID of this
part.
Writing to this register will configure
byte count and how many byte will
be read back. Do not write 00H to
this byte.
Writing to this register will configure
the number of seconds for the
watchdog timer to reset.
PWD Default
See individual
byte
description
See individual
byte
description
See individual
byte
description
08H
10H
Watchdog Control
Registers
10 Bit [6:0]
Watchdog enable, watchdog status
and programmable 'safe' frequency'
can be configured in this register.
000,0000
VCO Control Selection
Bit 10 Bit [7]
This bit select whether the output
frequency is control by
hardware/byte 0 configurations or
byte 11&12 programming.
0
VCO Frequency
Control Registers
Spread Spectrum
Control Registers
11-12
13-14
These registers control the dividers
ratio into the phase detector and
thus control the VCO output
frequency.
These registers control the spread
percentage amount.
Depended on
hardware/byte
0 configuration
Depended on
hardware/byte
0 configuration
Group Skews Control
Registers
15-16
Increment or decrement the group
skew amount as compared to the
initial skew.
See individual
byte
description
Output Rise/Fall Time
Select Registers
17-20
These registers will control the
output rise and fall time.
See individual
byte
description
Notes:
1. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches
for verification. Readback will support standard SMBUS controller protocol. The number of bytes to
readback is defined by writing to byte 8.
2. When writing to byte 11 - 12, and byte 13 - 14, they must be written as a set. If for example, only byte
14 is written but not 15, neither byte 14 or 15 will load into the receiver.
3. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
4. The input is operating at 3.3V logic levels.
5. The data byte format is 8 bit bytes.
6. To simplify the clock generator I2C interface, the protocol is set to use only Block-Writes from the
controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to
stop after any complete byte has been transferred. The Command code and Byte count shown above must
www.bDeasteanSt, hbuetetht4e Uda.tcaoismignored for those two bytes. The data is loaded until a Stop sequence is issued.
7. At power-on, all registers are set to a default condition, as shown.
0442C—07/03/02
5

5 Page





ICS94215 arduino
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ICS94215
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of the device at these or any other conditions above those
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70º C; Supply Volt age VDD = 3.3 V +/-5% (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP
Input High Voltage
VIH
2
Input Low Voltage
VIL
VSS-0.3
Input High Current
IIH
VIN = VDD
Input Low Current
IIL1
VIN =0 V; Inputs with no pull- -5
up resistors
Input Low Current
IIL2
VIN =0 V; Inputs with pull-up -200
resistors
IDD3.3OP66 CL =0 pF; Select@ 66MHz
87
MAX
VDD+0.3
0.8
5
UNITS
V
V
A
mA
Supply Current
IDD3.3OP100 CL =0 pF; Select@ 100MHz
IDD3.3OP133 CL =0 pF; Select@ 133MHz
91 180
104
Power Down
PD
3.25
Input frequency
Fi
VDD = 3.3 V
12 14.32
Input Capacitance1
CIN
CIN
Logic Inputs
Logic Inputs
CINX
X1 & X2 pins
27
TSTAB
From VDD= 3.3 V to 1% target
Freq.
tCPU-PCI
VT = 50% to 1.5V
1 Guaranteed by design, not 100% tested in production.
1 2.85
5
16
5
5
45
3
4
mA
mA
MHz
pF
pF
pF
ms
ns
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0442C—07/03/02
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