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PDF ICS94225 Data sheet ( Hoja de datos )
| Número de pieza | ICS94225 | |
| Descripción | AMD-K7TM System Clock Chip | |
| Fabricantes | Integrated Circuit Solution | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ICS94225 (archivo pdf) en la parte inferior de esta página. Total 18 Páginas | ||
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Integrated
Circuit
Systems, Inc.
ICS94225
AMD-K7TM System Clock Chip
Recommended Application:
AMD 750/760 style chipset
Output Features:
• 3 differential pair open drain CPU clocks (1.5V
external
pull-up; up to 150MHz achieviable through I2C)
• 2 - AGPCLK @ 3.3V
• 8 - PCI @3.3V, including 1 free running
• 1 - 48MHz @ 3.3V
• 1 - 24/48MHz @ 3.3V
• 2- REF @3.3V, 14.318MHz.
Features:
• Programmable ouput frequency
• Programmable ouput rise/fall time
• Programmable group skew
• Real time system reset output
• Spread spectrum for EMI control typically
by 7dB to 8dB,
with programmable spread percentage
• Watchdog timer technology to reset system
if over-clocking causes malfunction
• Uses external 14.318MHz crystal
Pin Configuration
**FS0/REF0
**FS1/REF1
GNDREF
X1
X2
GNDPCI
PCICLK_F
PCICLK0
VDDPCI
PCICLK1
PCICLK2
GNDPCI
PCICLK3
PCICLK4
VDDPCI
PCICLK5
PCICLK6
VDDAGP
AGP0
AGP1
GNDAGP
VDD48
48MHz
SEL24_48#/24-48MHz
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 VDDREF
47 GNDSD
46 SDRAM_OUT
45 VDDSD
44 RESERVED
43 CPUCLKC2
42 CPUCLKT2
41 GNDCPU
40 CPUCLKC1
39 CPUCLKT1
38 GND
37 CPUCLKC0
36 CPUCLKT0
35 RESET#
34 VDD
33 GND
32 PCI_STOP#
31 CPU_STOP#
30 PD#
29 SPREAD#
28 FS2*
27 SDATA
26 SCLK
25 GND48
48-Pin 300mil SSOP
* Internal 120K pullup resistor on indicated inputs
** Internal 240K pullup resistor on indicated inputs
Block Diagram
PLL2
X1 XTAL
X2 OSC
/2
PLL1
Spread
Spectrum
CPU
DIVDER
Stop
SEL24_48#
SDRAM
DIVDER
SDATA
SCLK
FS (2:0)
PD#
PCI_STOP#
Control
Logic
Config.
Reg.
PCI
DIVDER
AGP
DIVDER
CPU_STOP#
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Stop
0445B—08/01/03
48MHz
24_48MHz
REF (1:0)
3 CPUCLKT (2:0)
3 CPUCLKC (2:0)
SDRAM_OUT
PCICLK (6:0)
7
PCICLK_F
AGP (1:0)
2
Functionality
FS2 FS1 FS0
0 00
001
010
011
100
101
110
111
CPU,
SDRAM
133.33
95
100.99
115
100.7
103
105
110
Power Groups
VDD48, GND48 = 48MHz, PLL2
VDDREF, GNDREF= REF, X1, X2
VDD, GND = PLL Core
PCI
33.33
31.67
33.66
38.33
33.57
34.33
35.00
36.67
AGP
66.67
63.33
67.33
76.67
67.13
68.67
70.00
73.33
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ICS94225
Byte 7: Vendor ID and Revision ID Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PWD
Description
0 Vendor ID
0 Vendor ID
1 Vendor ID
X Revision ID
X Revision ID
X Revision ID
X Revision ID
X Revision ID
Byte 8: Byte Count and Read Back Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PWD
0 Reserved
0 Reserved
0 Reserved
0 Reserved
1 Reserved
0 Reserved
0 Reserved
0 Reserved
Description
Byte 9: Watchdog Timer Count Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PWD
Description
0
0 The decimal representation of these
0 8 bits correspond to 290ms or 1ms
0 the watchdog timer will wait before
0 it goes to alarm mode and reset the
0 frequency to the safe setting. Default
0 at power up is 290ms.
0
Byte 10: VCO Control Selection Bit &
Watchdog Timer Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PWD
Description
0 0=Hw/B0 freq / 1=B11 & 12 freq
0 WD Enable 0=disable / 1=enable
0 WD Status 0=normal / 1=alarm
1 WD Safe Frequency, Byte 0 bit 2
0 WD Safe Frequency, FS3
0 WD Safe Frequency, FS2
0 WD Safe Frequency, FS1
0 WD Safe Frequency, FS0
Note: FS values in bit [0:4] will correspond to Byte 0 FS
values. Default safe frequency is same as 00000
entry in byte0.
Byte 11: VCO Frequency Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PWD
Description
X VCO Divider Bit0
X REF Divider Bit6
X REF Divider Bit5
X REF Divider Bit4
X REF Divider Bit3
X REF Divider Bit2
X REF Divider Bit1
X REF Divider Bit0
Note: The decimal representation of these 7 bits (Byte 11
[6:0]) + 2 is equal to the REF divider value .
Notes:
1. PWD = Power on Default
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Byte 12: VCO Frequency Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PWD
Description
X VCO Divider Bit8
X VCO Divider Bit7
X VCO Divider Bit6
X VCO Divider Bit5
X VCO Divider Bit4
X VCO Divider Bit3
X VCO Divider Bit2
X VCO Divider Bit1
Note: The decimal representation of these 9 bits (Byte
12 bit [7:0] & Byte 11 bit [7] ) + 8 is equal to the VCO
divider value. For example if VCO divider value of 36
is desired, user need to program 36 - 8 = 28, namely, 0,
00011100 into byte 12 bit & byte 11 bit 7.
0445B—08/01/03
5
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ICS94225
Electrical Characteristics - AGP(1:0)
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
Output High Voltage
VOH5
IOH = -18 mA
Output Low Voltage
VOL5
IOL = 1.8 mA
Output High Current
IOH5
VOH = 2.0 V
Output Low Current
Rise Time1
Fall Time1
Duty Cycle1
Skew1 (window)
Jitter, Cycle-to-cycle1
IOL5
tr5
tf5
dt5
Tsk1
tjcyc-cyc2B
VOL = 0.8 V
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 50%
VT = 50%
VT = 50%
1Guaranteed by design, not 100% tested in production.
2.6
19
45
TYP
1.05
1.27
50.4
12
268
MAX
0.4
-16
1.6
1.6
55
200
500
UNITS
V
V
mA
mA
ns
ns
%
ps
ps
Electrical Characteristics - SDRAM_OUT
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Output High Voltage
VOH3
IOH = -11 mA
2
V
Output Low Voltage
VOL3
IOL = 11 mA
0.4 V
Output High Current
IOH3
VOH = 2.0 V
-12 mA
Output Low Current
IOL3
VOL = 0.8 V
12
mA
Rise Time1
tr3 VOL = 0.4 V, VOH = 2.4 V@100MHz
0.83 1.6
ns
Fall Time1
tf3 VOH = 2.4 V, VOL = 0.4 V@100MHz
0.71 1.6
ns
Duty Cycle1
dt3
VT = 50%
45 50.8 55
%
Jitter, Cycle-to-cycle1 tjcyc-cyc3B
VT = 50% @ 100MHz
240 250
ps
1Guaranteed by design, not 100% tested in production.
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0445B—08/01/03
11
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet ICS94225.PDF ] | |
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