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PDF ICS94203 Data sheet ( Hoja de datos )
| Número de pieza | ICS94203 | |
| Descripción | Programmable System Frequency Generator | |
| Fabricantes | Integrated Circuit Systems | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ICS94203 (archivo pdf) en la parte inferior de esta página. Total 18 Páginas | ||
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Integrated
Circuit
Systems, Inc.
ICS94203
Programmable System Frequency Generator for PII/III™
Recommended Application:
810/810E and Solano (815) type chipset
Output Features:
• 2 - CPUs @ 2.5V
• 13 - SDRAM @ 3.3V
• 3 - 3V66 @ 3.3V
• 7 - PCI @3.3V
• 1 - 24/48MHz@ 3.3V
• 1 - 48MHz @ 3.3V fixed
• 1 - REF @3.3V, 14.318MHz
Features:
• Programmable ouput frequency
• Gear ratio change detection
• Real time system reset output
• Spread spectrum for EMI control
with programmable spread percentage
• Watchdog timer technology to reset system
if over-clocking causes malfunction.
• Support power management through PD#.
• Uses external 14.318MHz crystal
• FS pins for frequency select
Key Specifications:
• CPU Output Jitter: <250ps
• IOAPIC Output Jitter: <500ps
• 48MHz, 3V66, PCI Output Jitter: <500ps
• CPU Output Skew: <175ps
• PCI Output Skew: <500ps
• 3V66 Output Skew <175ps
• For group skew timing, please refer to the
Group Timing Relationship Table.
Power Groups
VDDA, GNDA = Core PLL, Xtal
VDD48, GND48 = 48MHz, Fixed PLL
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Pin Configuration
VDDA
GNDA
X1
X2
GND3V66
VDD3V66
3V66-0
3V66-1
3V66-2
VDDPCI
GNDPCI
1*FS0/PCICLK0
1*FS1/PCICLK1
1*SEL24_48#/PCICLK2
GNDPCI
VDDPCI
PCICLK3
PCICLK4
PCICLK5
PCICLK6
RATIO_0
PD#
SCLK
SDATA
VDD48
GND48
*FS2/24_48MHz
1*FS3/48MHz
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56 REF/FS4*1
55 VDDLAPIC
54 IOAPIC01
53 VDDLCPU
52 GNDLCPU
51 CPUCLK0
50 CPUCLK1
49 GNDSDR
48 VDDSDR
47 SDRAM0
46 SDRAM1
45 SDRAM2
44 SDRAM3
43 VDDSDR
42 GNDSDR
41 SDRAM4
40 SDRAM5
39 SDRAM6
38 SDRAM7
37 SDRAM_F
36 GNDSDR
35 VDDSDR
34 SDRAM8
33 SDRAM9
32 SDRAM10
31 SDRAM11
30 RESET#
29 RATIO_1
56-Pin 300 mil SSOP
1. These pins will have 1.5 to 2X drive strength.
* 120K ohm pull-up to VDD on indicated inputs.
Block Diagram
PLL2
X1 XTAL
X2 OSC
PLL1
Spread
Spectrum
FS(4:0)
PD#
SEL24_48#
SDATA
SCLK
Control
Logic
Config.
Reg.
/2
CPU
DIVDER
SDRAM
DIVDER
IOAPIC
DIVDER
PCI
DIVDER
3V66
DIVDER
48MHz
24_48MHz
REF
2 CPUCLK (1:0)
12 SDRAM (11:0)
SDRAM_F
IOAPIC
PCICLK (6:0)
7
3V66 (2:0)
3
RESET#
RATIO_0
RATIO_1
94203 Rev B 02/13/01
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
1 page  
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ICS94203
Byte 0: Functionality and frequency select register (Default=0)
Bit
Description
PWD
Bit
(2,7:4)
Bit 3
Bit 1
Bit 0
Bit2 Bit7 Bit6 Bit5 Bit4 VCO/REF VCO VCO/ CPUCLK SDRAM
FS4 FS3 FS2 FS1 FS0 Divider MHz CPU MHz MHz
0 0 0 0 0 362/13 398.71 6
0 0 0 0 1 352/14 360.00 6
0 0 0 1 0 504/18 400.91 6
0 0 0 1 1 315/11 410.02 6
0 0 1 0 0 440/15 420.00 6
0 0 1 0 1 440/14 450.00 6
0 0 1 1 0 503/15 480.14 6
0 0 1 1 1 313/9 497.95 6
0 1 0 0 0 515/37 199.29 2
0 1 0 0 1 447/40 160.29 2
66.45
60.00
66.80
68.33
70.00
75.00
80.00
83.00
99.65
80.00
99.65
90.00
100.20
102.50
105.00
112.50
120.00
124.50
99.65
80.00
0 1 0 1 0 518/37 200.45 2 100.23 100.23
0 1 0 1 1 446/31 206.00 2 103.00 103.00
0 1 1 0 0 484/33 210.00 2 105.00 105.00
0 1 1 0 1 507/33 219.98 2 110.00 110.00
0 1 1 1 0 514/32 229.99 2 115.00 115.00
0 1 1 1 1 461/11 600.06 2 200.00 200.00
1 0 0 0 0 362/13 398.71 3 132.86 132.86
1 0 0 0 1 503/15 480.14 3 160.00 160.00
1 0 0 1 0 504/18 400.91 3 133.64 133.64
1 0 0 1 1 488/17 411.02 3 137.00 137.00
1 0 1 0 0 440/15 420.00 3 140.00 140.00
1 0 1 0 1 395/13 435.05 3 145.00 145.00
1 0 1 1 0 440/14 450.00 3 150.00 150.00
1 0 1 1 1 503/15 480.14 3 160.00 160.00
1 1 0 0 0 362/13 398.71 3 132.90 99.65
1 1 0 0 1 503/15 480.14 3 160.00 100.00
1 1 0 1 0 504/18 400.91 3 133.64 100.23
1 1 0 1 1 488/17 411.02 3 137.00 102.75
1 1 1 0 0 440/15 420.00 3 140.00 105.00
1 1 1 0 1 395/13 435.05 3 145.00 108.75
1 1 1 1 0 440/14 450.00 3 150.00 112.50
1 1 1 1 1 503/15 480.14 3
0-Frequency is selected by hardware select, latched inputs
1- Frequency is selected by Bit 2,7:4
0- Normal
1- Spread spectrum enable ± 0.35% Center Spread
160.00 120.00
0- Running
1- Tristate all outputs
3V66
MHz
66.43
60.00
66.80
68.33
70.00
75.00
80.00
83.00
66.43
53.33
66.84
68.67
70.00
73.33
76.67
100.00
66.43
80.00
66.82
68.50
70.00
72.50
75.00
80.00
66.93
80.00
66.82
68.50
70.00
72.50
75.00
80.00
PCICLK IOAPIC
MHz MHz
33.21
30.00
33.40
34.17
35.00
37.50
40.00
41.50
33.21
26.67
33.41
34.33
35.00
36.67
38.33
50.00
33.21
40.00
33.41
34.25
35.00
36.25
37.50
40.00
33.21
40.00
33.41
34.25
35.00
36.25
37.50
40.00
16.61
15.00
16.70
17.08
17.50
18.75
20.00
20.75
16.61
13.33
16.70
17.17
17.50
18.33
19.17
25.00
16.61
20.00
16.70
17.13
17.50
18.13
18.75
20.00
16.61
20.00
16.7
17.13
17.50
18.13
18.75
20.00
Note 1
0
1
0
N1w.oDtweeswf:a.uDltaattapSowheer-eutp4wUil.lcboemfor latched logic inputs to define frequency, as displayed by Bit 3.
5
5 Page 
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ICS94203
Absolute Maximum Ratings
Core Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . 4.6 V
I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 3.6V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 115°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress
specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections
of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product
reliability.
Group Timing Relationship Table1
Group
CPU to SDRAM
CPU to 3V66
SDRAM to 3V66
CPU 66MHz
SDRAM 100MHz
Offset Tolerance
2.5ns 500ps
7.5ns 500ps
0.0ns 500ps
CPU 100MHz
SDRAM 100MHz
Offset Tolerance
5.0ns 500ps
5.0ns 500ps
0.0ns 500ps
CPU 133MHz
SDRAM 100MHz
Offset Tolerance
0.0ns 500ps
0.0ns 500ps
0.0ns 500ps
CPU 133MHz
SDRAM 133MHz
Offset Tolerance
3.75ns 500ps
0.0ns 500ps
3.75ns 500ps
3V66 to PCI
PCI to PCI
USB & DOT
1.5-3.5ns
0.0ns
Asynch
500ps
1.0ns
N/A
1.5-3.5ns
0.0ns
Asynch
500ps
1.0ns
N/A
1.5-3.5ns
0.0ns
Asynch
500ps
1.0ns
N/A
1.5 -3.5ns
0.0ns
Asynch
500ps
1.0ns
N/A
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70º C; Supply Volt age VDD = 3.3 V +/-5% (unless otherwise stated)
PARAMETER SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Input High Voltage
VIH
2 VDD+0.3
Input Low Voltage
VIL
VSS-0.3
0.8
Input High Current
IIH
VIN = VDD
5
Input Low Current
IIL1 VIN=0 V;Inputs with no pull-up resistors -5
Input Low Current IIL2 VIN=0 V; Inputs with pull-up resistors -200
Supply Current IDD3.3OP100
CL=30 pF
346 400
Power Down
PD
4.3 600
V
V
A
uA
uA
mA
mA
Input frequency
Fi
VDD = 3.3 V;
CIN Logic Inputs
Input Capacitance1
CIN
Logic Inputs
Clk Stabilization1
CINX
TSTAB
X1 & X2 pins
From VDD= 3.3 V to 1% target Freq.
1 Guaranteed by design, not 100% tested in production.
12 14.318
27
16
5
5
45
3
MHz
pF
pF
pF
ms
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11
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| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet ICS94203.PDF ] | |
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