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PDF D74HC08C Data sheet ( Hoja de datos )
| Número de pieza | D74HC08C | |
| Descripción | CD74HC08C | |
| Fabricantes | ETC | |
| Logotipo |  |
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Data sheet acquired from Harris Semiconductor
SCHS118
August 1997
CD54HC08, CD54HCT08,
CD74HC08, CD74HCT08
High Speed CMOS Logic
Features
Description
• Buffered Inputs
[ /Title
(CD54H
•
Typical Propagation Delay:
CL = 15pF, TA = 25oC
7ns
at
VCC
=
5V,
C08,
• Fanout (Over Temperature Range)
CD54H
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
CwwTw0.D8a,taSheet4U.-coBmus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
CD74H
• Wide Operating Temperature Range . . . -55oC to 125oC
C08,
CD74H
CT08)
/Sub-
ject
(High
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
• CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH
The Harris CD54HC08, CD54HCT08, CD74HC08 and
CD74HCT08 logic gates utilize silicon gate CMOS
technology to achieve operating speeds similar to LSTTL
gates with the low power consumption of standard CMOS
integrated circuits. All devices have the ability to drive 10
LSTTL loads. The 74HCT logic family is functionally pin
compatible with the standard 74LS logic family.
Ordering Information
TEMP. RANGE
PART NUMBER
(oC)
PACKAGE
PKG.
NO.
CD74HC08E
-55 to 125 14 Ld PDIP
E14.3
CD74HCT08E
-55 to 125 14 Ld PDIP
E14.3
CD74HC08M
-55 to 125 14 Ld SOIC
M14.15
CD74HCT08M
-55 to 125 14 Ld SOIC
M14.15
CD54HC08F
-55 to 125 14 Ld CERDIP F14.3
CD54HCT08F
-55 to 125 14 Ld CERDIP F14.3
CD54HC08W
-55 to 125 Wafer
CD54HCT08W
-55 to 125 Wafer
CD54HC08H
-55 to 125 Die
CD54HCT80H
-55 to 125 Die
NOTE:
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
Pinout
CD54HC08, CD54HCT08, CD74HC08, CD74HCT08
(PDIP, CERDIP, SOIC)
TOP VIEW
1A 1
1B 2
1Y 3
2A 4
2B 5
2Y 6
GND 7
14 VCC
13 4B
12 4A
11 4Y
10 3B
9 3A
8 3Y
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1997
1
File Number 1549.1
1 page  
CD54HC08, CD54HCT08, CD74HC08, CD74HCT08
Switching Specifications Input tr, tf = 6ns (Continued)
PARAMETER
TEST
VCC
25oC
-40oC TO 85oC -55oC TO 125oC
SYMBOL CONDITIONS (V) MIN TYP MAX MIN MAX MIN MAX UNITS
Transition Times (Figure 1)
tTLH, tTHL CL = 50pF
2 - - 75
-
95
- 110 ns
4.5 -
- 15
-
19
-
22 ns
6 - - 13
-
16
-
19 ns
Input Capacitance
Power Dissipation Capacitance
(Note 3, 4)
CI
CPD
-
- - - 10
-
10
-
10 pF
-
5 - 37 -
-
-
-
- pF
HCT TYPES
Propagation Delay, Input to
tPLH, tPHL CL = 50pF
4.5 -
- 25
-
31
-
38 ns
www.DataSheet4UO.uctopmut Y (Figure 2)
Propagation Delay, Data Input to tPLH, tPHL CL = 15pF
5 - 10 -
-
-
-
- ns
Output Y
Transition Times (Figure 2)
tTLH, tTHL CL = 50pF
4.5 -
- 15
-
19
-
22 ns
Input Capacitance
CI CL = 50pF
- - - 10
-
10
-
10 pF
Power Dissipation Capacitance
(Notes 3, 4)
CPD
-
5 - 51 -
-
-
-
- pF
NOTES:
3. CPD is used to determine the dynamic power consumption, per gate.
4. PD = VCC2 fi (CPD + CL) where fi = input frequency, CL = output load capacitance, VCC = supply voltage.
Test Circuits and Waveforms
tr = 6ns
INPUT
90%
50%
10%
tf = 6ns
VCC
GND
tTHL
INVERTING
OUTPUT
tPHL
tTLH
90%
50%
10%
tPLH
FIGURE 3. HC AND HCU TRANSITION TIMES AND PROPAGA-
TION DELAY TIMES, COMBINATION LOGIC
tr = 6ns
INPUT
2.7V
1.3V
0.3V
tf = 6ns
3V
GND
tTHL
INVERTING
OUTPUT
tPHL
tTLH
90%
1.3V
10%
tPLH
FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
5
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet D74HC08C.PDF ] | |
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