PDF ICS570B Data sheet ( Hoja de datos )

Número de pieza	ICS570B
Descripción	Multiplier and Zero Delay Buffer
Fabricantes	Integrated Circuit Systems
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No Preview Available ! www.DataSheet4U.com PRELIMINARY INFORMATION ICS570B Multiplier and Zero Delay Buffer Description The ICS570B is a high performance Zero Delay Buffer (ZDB) which integrates ICS’ proprietary analog/digital Phase Locked Loop (PLL) techniques. The ICS570B, part of ICS’ ClockBlocks™ family, was designed as a performance upgrade to meet today’s higher speed and lower voltage requirements. The zero delay feature means that the rising edge of the input clock aligns with the rising edges of both outputs, giving the appearance of no delay through the device. There are two outputs on the chip, one being a low-skew divide by two of the other. The device incorporates an all-chip power down/tri-state mode that stops the internal PLL and puts both outputs into a high impedance state. The ICS570B is ideal for synchronizing outputs in a large variety of systems, from personal computers to data communications to graphics/video. By allowing off-chip feedback paths, the device can eliminate the delay through other devices. The ICS570B was done to improve input to output jitter from the original ICS570M and ICS570A verisons, and is recommended for all new 3.3 V only designs. For 5V applications, use the ICS570A. Features • Packaged in 8 pin SOIC. • Pin-for-pin replacement and upgrade to ICS570/ICS570A • Functional equivalent to AV9170 (not a pin- for-pin replacement). • Low input to output skew of 300 ps max (>60 MHz outputs). • Low skew (100 ps) outputs. • Ability to choose between 14 different multipliers from 0.5X to 32X. • Input clock frequency up to 150 MHz at 3.3V. • Can recover degraded input clock duty cycle. • Output clock duty cycle of 45/55. • Power Down and Tri-State Mode. • Full CMOS clock swings with 25mA drive capability at TTL levels. • Advanced, low power CMOS process. • Operating voltage of 3.3 V (±5%). • Industrial temperature version available Block Diagram ICLK S1, S0 FBIN 2 divide by N Phase Detector, Charge Pump, and Loop Filter Voltage Controlled Oscillator ÷2 Output Buffer Output Buffer CLK CLK/2 External feedback can come from CLK or CLK/2 (see table on page 2). www.DataSheet4U.com MDS 570B A 1 Revision 053001 Integrated Circuit Systems, Inc . • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel • www.icst.com 1 page www.DataSheet4U.com PRELIMINARY INFORMATION ICS570B Multiplier and Zero Delay Buffer Recommended Circuit: S1 VDD GND INPUT FBIN S0 CLK CLK/2 ICLK CLK CLK/2 x2 Mode (S1, S0 = 1, 1) CLK Feedback ICK CLK CLK/2 x2 Mode (S1, S0 = 1, 0) CLK/2 Feedback Using CLK as the feedback will always result in synchronized rising edges between ICLK and CLK. However, the CLK/2 could be a falling edge compared with ICLK. Therefore, whenever possible, we recommend the use of CLK/2 feedback. This will synchronize the rising edges of all 3 clocks. www.DataSheet4U.com MDS 570B A 5 Revision 053001 Integrated Circuit Systems, Inc . • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel • www.icst.com 5 Page

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