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PDF CDB44600 Data sheet ( Hoja de datos )
| Número de pieza | CDB44600 | |
| Descripción | 6-Channel Digital Amplifier Controller | |
| Fabricantes | Cirrus Logic | |
| Logotipo |  |
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CS44600
6-Channel Digital Amplifier Controller
Features
> 100 dB Dynamic Range - System Level
< 0.03% THD+N @ 1 W - System Level
32 kHz to 192 kHz Sample Rates
Internal Oscillator Circuit Supports 24.576 MHz
to 54 MHz Crystals
Integrated Sample Rate Converter (SRC)
– Eliminates Clock Jitter Effects
– Input Sample Rate Independent Operation
Power Supply Rejection Realtime Feedback
Spread Spectrum Modulation - Reduces
Modulation Energy
PWM PopGuard® for Single-Ended Mode
Eliminates AM Frequency Interference
Programmable Load Compensation Filters
Support for up to 40 kHz Audio Bandwidth
Digital Volume Control with Soft Ramp
– +24 to -127 dB in 0.25 dB Steps
Per Channel Programmable Peak Detect and
Limiter
SPI and I²C Host Control Interfaces
Separate 2.5 V to 5.0 V Serial Port and Host
Control Port Supplies
PS_SYNC
XTI
XTO
SYS_CLK
DAI_MCLK
DAI_SCLK
DAI_LRCK
DAI_SDIN1
DAI_SDIN2
DAI_SDIN3
MUTE
SCL/CCLK
SDA/CDOUT
AD1/CDIN
AD0/CS
RST
INT
PWM
Clock
Control
Auto Fs
Detect
DAI
Serial
Port
SRC
Volume
/ Limiter
Volume
/ Limiter
Volume
/ Limiter
Multibit
Σ∆
Modulator
Multibit
Σ∆
Modulator
Multibit
Σ∆
Modulator
Power
Supply
Rejection
PWM
Conversion
PWM
Conversion
PWM
Conversion
PSR_RESET
PSR_EN
PSR_MCLK
PSR_SYNC
PSR_DATA
PWMOUTA1+
PWMOUTA1-
PWMOUTB1+
PWMOUTB1-
PWMOUTA2+
PWMOUTA2-
PWMOUTB2+
PWMOUTB2-
PWMOUTA3+
PWMOUTA3-
PWMOUTB3+
PWMOUTB3-
SPI/I2C Host
Control Port
PWM
Backend
Control/
Status
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
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Preliminary Product Information This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
http://www.cirrus.com
Copyright © Cirrus Logic, Inc. 2005
(All Rights Reserved)
MAY '05
DS633PP1
1 page  
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CS44600
7.19.1 Channel Compensation Filter - Fine Adjust (CHXX_FINE[5:0]) ........................ 61
7.20 Interrupt Mode Control (address 28h) ........................................................................... 61
7.20.1 Interrupt Pin Control (INT1/INT0) ...................................................................... 61
7.20.2 Overflow Level/Edge Select (OVFL_L/E) .......................................................... 62
7.21 Interrupt Mask (address 29h) ........................................................................................ 62
7.22 Interrupt Status (address 2Ah) (Read Only) ................................................................. 62
7.22.1 SRC Unlock Interrupt (SRC_UNLOCK) ............................................................ 62
7.22.2 SRC Lock Interrupt (SRC_LOCK) ..................................................................... 63
7.22.3 Ramp-Up Complete Interrupt (RMPUP_DONE) ............................................... 63
7.22.4 Ramp-Down Complete Interrupt (RMPDN_DONE) .......................................... 63
7.22.5 Mute Complete Interrupt (Mute_DONE) ........................................................... 63
7.22.6 Channel Over Flow Interrupt (OVFL_INT) ........................................................ 63
7.22.7 GPIO Interrupt Condition (GPIO_INT) .............................................................. 63
7.23 Channel Over Flow Status (address 2Bh) (Read Only) ................................................. 64
7.23.1 ChXX_OVFL ..................................................................................................... 64
7.24 GPIO Pin In/Out (address 2Ch) ..................................................................................... 64
7.24.1 GPIO In/Out Selection (GPIOX_I/O) ................................................................. 64
7.25 GPIO Pin Polarity/Type (address 2Dh) .......................................................................... 64
7.25.1 GPIO Polarity/Type Selection (GPIOX_P/T) ..................................................... 64
7.26 GPIO Pin Level/Edge Trigger (address 2Eh) ................................................................. 65
7.26.1 GPIO Level/Edge Input Sensitive (GPIOX_L/E) ............................................... 65
7.27 GPIO Status Register (address 2Fh) ............................................................................. 65
7.27.1 GPIO Pin Status (GPIOX_STATUS) ................................................................. 65
7.28 GPIO Interrupt Mask Register (address 30h) ................................................................ 66
7.28.1 GPIO Pin Interrupt Mask (M_GPIOX) ............................................................... 66
7.29 PWM Configuration Register (address 31h) ................................................................. 66
7.29.1 Over Sample Rate Selection (OSRATE) .......................................................... 66
7.29.2 Channels A1 and B1 Output Configuration (A1/B1_OUT_CNFG) .................... 66
7.29.3 Channels A2 and B2 Output Configuration (A2/B2_OUT_CNFG) .................... 66
7.29.4 Channel A3 Output Configuration (A3_OUT_CNFG) ....................................... 67
7.29.5 Channel B3 Output Configuration (B3_OUT_CNFG) ....................................... 67
7.30 PWM Minimum Pulse Width Register (address 32h) .................................................... 67
7.30.1 Disable PWMOUTXX - Signal (DISABLE_PWMOUTXX-) ................................ 67
7.30.2 Minimum PWM Output Pulse Settings (MIN_PULSE[4:0]) ............................... 67
7.31 PWMOUT Delay Register (address 33h) ...................................................................... 68
7.31.1 Differential Signal Delay (DIFF_DLY[2:0]) ........................................................ 68
7.31.2 Channel Delay Settings (CHNL_DLY[4:0]) ...................................................... 68
7.32 PSR and Power Supply Configuration (address 34h) .................................................... 69
7.32.1 Power Supply Rejection Enable (PSR_EN) ...................................................... 69
7.32.2 Power Supply Rejection Reset (PSR_RESET) ................................................. 70
7.32.3 Power Supply Rejection Feedback Enable (FEEDBACK_EN) ......................... 70
7.32.4 Power Supply Sync Clock Divider Settings (PS_SYNC_DIV[2:0]) ................... 70
7.33 Decimator Shift/Scale (addresses 35h, 36h, 37h) ......................................................... 70
7.33.1 Decimator Shift (DEC_SHIFT[2:0]) ................................................................... 70
7.33.2 Decimator Scale (DEC_SCALE[18:0]) .............................................................. 71
7.34 Decimator Outd (addresses 3Bh, 3Ch, 3Dh) ................................................................. 71
7.34.1 Decimator Outd (DEC_OUTD[23:0]) ................................................................. 71
8. PARAMETER DEFINITIONS .................................................................................................. 72
9. REFERENCES ........................................................................................................................ 74
10. PACKAGE DIMENSIONS
........................................................................................... 75
11. THERMAL CHARACTERISTICS ......................................................................................... 76
12. REVISION HISTORY ............................................................................................................ 77
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DS633PP1
5
5 Page 
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CS44600
PWM FILTER CHARACTERISTICS
(Logic “0” = GND = 0 V; Logic “1” = VLS = VLC; VD = 2.5 V; DAI_MCLK = 12.288 MHz; XTAL = 24.576 MHz; PWM
Switch Rate = 384 kHz; Fs = 32 kHz to 192 kHz; Measurement bandwidth is 10 Hz to 20 kHz unless otherwise
specified.)
Parameter
Digital Filter Response (Note 12)
Passband
OSRATE = 0b
OSRATE = 1b (Note 13)
OSRATE = 0b
OSRATE = 1b (Note 13)
Group Delay
De-emphasis Error
(Relative to 1 kHz)
to -0.01 dB corner
to -3 dB corner
to -0.01 dB corner
to -3 dB corner
Frequency Response
10 Hz to 20 kHz
10 Hz to 40 kHz
Fs = 32 kHz
Fs = 44.1 kHz
Fs = 48 kHz
Min
0
0
0
0
-0.8
-1.2
-
-
-
Typ Max
-
-
-
-
-
-
(Note 14)
-
-
-
1.6
24.0
3.3
44.5
+0.02
+0.02
±0.23
±0.14
±0.09
Unit
kHz
kHz
kHz
kHz
dB
dB
ms
dB
dB
dB
12. Filter response is not production tested but is characterized and guaranteed by design.
13. XTAL = 49.152 MHz; PWM Switch Rate = 768 kHz; Fs = 96 kHz to 192 kHz.
14. The equation for the group delay through the sample rate converter with OSRATE = 0b is (8.5 / Fsi) + (10
/ Fso) ± (4.5 / Fsi). The equation for the group delay through the sample rate converter with OSRATE = 1b
is (8.5 / Fsi) + (20 / Fso) ± (4.5 / Fsi).
SWITCHING CHARACTERISTICS - XTI
(VD = 2.5 V, VDP = VLC = VLS = 3.3 V, VDX = 2.5 V to 5.0 V; Inputs: Logic 0 = GND, Logic 1 = VDX)
Parameter
XTI period
XTI high time
XTI low time
XTI Duty Cycle
External Crystal operating frequency
Symbol
tclki
tclkih
tclkil
Min
18.518
8.34
8.34
45
24.576
Typ
---
---
---
50
---
Max
40.69
22.38
22.38
55
54
XTI
tclkih
tclkil
tclki
Figure 2. XTI Timings
Unit
ns
ns
ns
%
MHz
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DS633PP1
11
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CDB44600.PDF ] | |
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