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PDF DM9102D Data sheet ( Hoja de datos )
| Número de pieza | DM9102D | |
| Descripción | SINGLE CHIP FAST ETHEMET NIC CONTROLLER | |
| Fabricantes | DAVICOM | |
| Logotipo |  |
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DM9102D
Single Chip Fast Ethernet NIC Controller
1. General Description
The DM9102D is a fully integrated and cost effective single
chip Fast Ethernet NIC controller. It is designed with low
power and high performance process. It is a 2.5/3.3V device
with 5V tolerance.
The DM9102D provides direct interface to the PCI bus and
supports bus master mode to achieve the high performance
of the PCI bus. It fully complies with PCI 2.2. In the media
side, the DM9102D interfaces to the UTP3, 4, 5 in 10Base-T
and the UTP5 in 100Base-TX. It is fully compliant with the
IEEE 802.3u Spec. The auto-negotiation and
auto-MDI/MDIX function can automatically configure the
2. Block Diagram
DM9102D to take the maximum advantage of its abilities.
The DM9102D also supports IEEE 802.3x’s full-duplex flow
control to prevent the receive overflow of link partner. The
IPv4 IP/TCP/UDP checksum generation and checking can
reduce the system CPU utilization.
The DM9102D supports two types of power management
mechanisms. The main mechanism is based on the OnNow
architecture, which is required for PC99. The alternative
mechanism is based upon the remote Wake-On-LAN
mechanism.
Preliminary datasheet
Vwerswionw: D.MD91a02tDa-DSSh-P0e2et4U.com
Jan. 14, 2005
1
1 page  
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4. Pin Configuration : 128 pin LQFP
X2
X1/OSC
DGND
AGND
BGRESG
BGRES
AVDD25
AVDD25
RXI+
RXI-
AGND
AGND
TXO+
TXO-
AVDD25
AVDD25
INT#
RST#
PCICLK
ISOLATE#
GNT#
REQ#
PME#
DVDD25
AD31
AD30
AD29
AD28
DGND
AD27
AD26
AD25
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
DM9102D
64 MD2
63 MD1
62 MD0/EEDI
61 DVDD
60 AD0/MA0
59 AD1/MA1
58 DGND
57 AD2/MA2
56 AD3/MA3
55 AD4/MA4
54 AD5/MA5
53 DVDD
52 DVDD
51 AD6/MA6
50 AD7/MA7
49 AD8/MA8
48 CBE0#
47 AD9/MA9
46 DGND
45 DGND
44 AD10/MA10
43 AD11/MA11
42 DVDD
41 AD12/MA12
40 AD13/MA13
39 AD14/MA14
38 AD15/MA15
37 TEST1
36 CLOCKRUN#
35 DGND
34 CBE1#
33 PAR
Preliminary datasheet
Vwerswionw: D.MD91a02tDa-DSSh-P0e2et4U.com
Jan. 14, 2005
5
5 Page 
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6. Register Definition
6.1 PCI Configuration Registers
The definitions of PCI Configuration Registers are based on
the PCI specification revision 2.2 and it provides the
initialization and configuration information to operate the PCI
interface in the DM9102D. All registers can be accessed
with byte, word, or double word mode. As defined in PCI
specification 2.1, read accesses to reserve or
unimplemented registers will return a value of “0.” These
registers are to be described in the following sections.
The default value of PCI configuration registers after reset.
Description
Identifier
Identification
PCIID
Command & Status
PCICS
Revision
PCIRV
Miscellaneous
PCILT
I/O Base Address
PCIIO
Memory Base Address
PCIMEM
Reserved
--------
Subsystem Identification
PCISID
Expansion ROM Base Address
PCIROM
Capability Pointer
CAP_PTR
Reserved
--------
Interrupt & Latency
PCIINT
Device Specific Configuration Register PCIUSR
Power Management Register
PCIPMR
Power Management Control & Status PMCSR
* It is written to 02100007H by most BIOS.
** It may be changed from EEPROM in application.
Address Offset
00H
04H
08H
0CH
10H
14H
18H - 28H
2CH
30H
34H
38H
3CH
40H
50H
54H
Value of Reset
91021282H
02100000H*
02000050H
BIOS determine
System allocate
System allocate
00000000H
load from EEPROM
00000000H
00000050H
00000000H
System allocate bit7~0
00000000H**
C0310001H**
00000100H
Key to Default
In the register description that follows, the default column
takes the form <Reset Value>
Where
<Reset Value>:
1 Bit set to logic one
0 Bit set to logic zero
X No default value
<Access Type>:
RO = Read only
RW = Read/Write
R/C: means Read / Write & Write "1" for Clear.
Preliminary datasheet
Vwerswionw: D.MD91a02tDa-DSSh-P0e2et4U.com
Jan. 14, 2005
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet DM9102D.PDF ] | |
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