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PDF DM9102A Data sheet ( Hoja de datos )
| Número de pieza | DM9102A | |
| Descripción | Single Chip Fast Ethernet NIC controller | |
| Fabricantes | DAVICOM | |
| Logotipo |  |
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General Description
The DM9102A is a fully integrated and cost-effective single
chip Fast Ethernet NIC controller. It is designed with the low
power and high performance process. It is a 3.3V device
with 5V tolerance then it supports 3.3V and 5V signaling.
The DM9102A provides direct interface to the PCI or the
CardBus. It supports bus master capability and fully
complies with PCI 2.2. In media side, The DM9102A
interfaces to the UTP3,4,5 in 10Base-T and UTP5 in
100Base-TX. It is fully compliance with the IEEE 802.3u
DM9102A
Single Chip Fast Ethernet NIC controller
Spec. Its auto-negotiation function will automatically
configure the DM9102A to take the maximum advantage of
its abilities. The DM9102A is also support IEEE 802.3x full-
duplex flow control.
The DM9102A supports two types of power-management
mechanisms. The main mechanism is based upon the
OnNow architecture, which is required for PC99. The
alternative mechanism is based upon the remote Wake-On-
LAN mechanism.
Block Diagram
TX+/-
RX+/-
EEPROM
Interface
Boot ROM /
MII Interface
DMA
NRZI to MLT3
PHYceiver
NRZ to NRZI
Parallel to
Serial
Scrambler
4B/5B
Encoding
AEQ MLT3 to NRZI
NRZI to NRZ
Parallel to
Serial
De-
Scrambler
4B/5B
Decoding
MAC
TX
Machine
TX
FIFO
MII
RX
Machine
RX
FIFO
PCI
Interface
LED Driver
Autonegotiation
MII Management Control
& MII Register
Power
Management
Block
PME#
WOL
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Version: DM9102A-DS-F03
August 28, 2000
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Pin Configuration : 128 pin QFP
DM9102A
Single Chip Fast Ethernet NIC controller
AVDD
AVDD
RXI+
RXI-
AGND
AGND
TXO+
TXO-
AVDD
AVDD
INT#
RST#
PCICLK
ISOLATE#
GNT#
REQ#
PME#
DVDD
AD31
AD30
AD29
AD28
DGND
AD27
AD26
AD25
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
DM9102A
64 BPAD2 (MD2)
63 BPAD1 (MD1)
62 BPAD0 (MD0/EEDI)
61 DVDD
60 AD0
59 AD1
58 DGND
57 AD2
56 AD3
55 AD4
54 AD5
53 DVDD
52 DVDD
51 AD6
50 AD7
49 AD8
48 CBE0#
47 AD9
46 DGND
45 DGND
44 AD10
43 AD11
42 DVDD
41 AD12
40 AD13
39 AD14
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Version: DM9102A-DS-F03
August 28, 2000
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79
80
81
83,84,85
87
88
89
90
91,92,93,
94
DM9102A
Single Chip Fast Ethernet NIC controller
When The DM9102A will use this pin to serially write
opcodes, addresses and data into the EEPROM.
MA4/EECK
O Boot ROM address output/EEPROM serial clock
This is multiplexed pin used by MA4 and EECK .
This pin provides the clock for the EEPROM data transfer.
MA5
O Boot ROM address output signal
MA6/SELROM O/LI Boot ROM address output/Multiplex or Direct mode selection
This multiplexed pin acts as boot ROM address output bus
during normal operation. When RST# is active, it is used as
multiplex and direct mode selection :
0 = Boot ROM interface is in multiplex mode (default)
1 = Boot ROM interface is in direct mode.
MA7~MA9
O Boot ROM address output bus
MA10/LINK&ACT# O Boot ROM address output signal/Link & Active LED
In DIR mode, this pin represents the Boot ROM address bit
10 when at the time of boot ROM operation. When Boot
ROM is not accessed, this pin acts as traffic-and- link led in
LED MODE 0 or traffic led in LED MODE 1.
MA11/FDX#
O Boot ROM address output/Full-duplex LED
In DIR mode, this pin represents the Boot ROM address bit
11 when at the time of boot ROM operation. When Boot
ROM is not accessed, this pin acts as full-duplex led.
MA12 /
O Boot ROM address output/ 100Mbps LED
SPEED100#
In DIR mode, this pin represents the Boot ROM address bit
12 when at the time of boot ROM operation. When Boot
ROM is not accessed, this pin acts as speed-100 led.
MA13/SPEED10# O Boot ROM address output signal/10Mbps LED
In DIR mode, this pin represents the Boot ROM address bit
13 when at the time of boot ROM operation. When Boot
ROM is not accessed, this pin acts as speed-10 led.
MA14~MA17
O Boot ROM address output bus
LED Pins (Please refer to p.11 “NOTE: LED Mode” for details.)
Pin No.
Pin Name
I/O
Description
128QFP/128TQFP
87
LINK&ACT#
O LED output pin, active low
/ ACT#
mode 0 = Link and traffic LED. Active low to indicate normal
link, and it will flash as a traffic LED when transmitting or
receiving.
mode 1 = traffic LED only
88
FDX#
O LED output pin, active low
/ FDX#
mode 0 = Full duplex LED
mode 1 = Full duplex LED
89
SPEED100#
O LED output pin, active low
/ SPEED100#
mode 0 = 100Mbps LED
mode 1 = 100Mbps LED
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Version: DM9102A-DS-F03
August 28, 2000
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| PDF Descargar | [ Datasheet DM9102A.PDF ] | |
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