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PDF P-80C32 Datasheet ( Hoja de datos )

Número de pieza P-80C32
Descripción (P-80C32 / P-80C52) CMOS 8-Bit Microcontroller
Fabricantes Temic 
Logotipo Temic Logotipo

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P-80C32 Hoja de datos, Descripción, Manual
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80C32/80C52
CMOS 0 to 44 MHz Single Chip 8–bit Microcontroller
1. Description
TEMIC’s 80C52 and 80C32 are high performance
CMOS versions of the 8052/8032 NMOS single chip 8
bit Microcontroller.
The fully static design of the TEMIC 80C52/80C32
allows to reduce system power consumption by bringing
the clock frequency down to any value, even DC,
without loss of data.
The 80C52 retains all the features of the 8052: 8 K bytes
of ROM; 256 bytes of RAM; 32 I/O lines; three 16 bit
timers; a 6-source, 2-level interrupt structure; a full
duplex serial port; and on-chip oscillator and clock
circuits. In addition, the 80C52 has 2
D 80C32: Romless version of the 80C52
D 80C32/80C52-L16: Low power version
VCC: 2.7 – 5.5 V Freq: 0-16 MHz
D 80C32/80C52-12: 0 to 12 MHz
D 80C32/80C52-16: 0 to 16 MHz
D 80C32/80C52-20: 0 to 20 MHz
D 80C32/80C52-25: 0 to 25 MHz
D 80C32/80C52-30: 0 to 30 MHz
D 80C32/80C52-36: 0 to 36 MHz
software-selectable modes of reduced activity for
further reduction in power consumption. In the idle
mode the CPU is frozen while the RAM, the timers, the
serial port and the interrupt system continue to function.
In the power down mode the RAM is saved and all other
functions are inoperative.
The 80C32 is identical to the 80C52 except that it has no
on-chip ROM. TEMIC’s 80C52/80C32 are
manufactured using SCMOS process which allows them
to run from 0 up to 44 MHz with VCC = 5 V.
TEMIC’s 80C52 and 80C32 are also available at
16 MHz with 2.7 V < VCC < 5.5 V.
D 80C32-40: 0 to 40 MHz(1)
D 80C32-42: 0 to 42 MHz(1)
D 80C32-44: 0 to 44 MHz(1)
Notes:
1. 0 to 70_C temperature range.
2. For other speed and temperature range availability, please
contact your sales office.
2. Features
D Power control modes
D 256 bytes of RAM
D 8 Kbytes of ROM (80C52)
D 32 programmable I/O lines
D Three 16 bit timer/counters
D 64 K program memory space
D 64 K data memory space
D Fully static design
D 0.8µ CMOS process
D Boolean processor
D 6 interrupt sources
D Programmable serial port
D Temperature range: commercial, industrial, automotive,
military
3. Optional
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D Secret ROM: Encryption
D Secret TAG: Identification number
Rev. I September 18, 1998
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P-80C32 pdf
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80C32/80C52
Port Pin
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
Alternate Function
RXD (serial input port)
TXD (serial output port)
INT0 (external interrupt 0)
INT1 (external interrupt 1)
TD (Timer 0 external input)
T1 (Timer 1 external input)
WR (external Data Memory write strobe)
RD (external Data Memory read strobe)
Port 3 can sink/source three LS TTL inputs. It can drive CMOS inputs without external pullups.
5.7. RST
A high level on this for two machine cycles while the oscillator is running resets the device. An internal pull-down
resistor permits Power-On reset using only a capacitor connected to VCC. As soon as the Reset is applied (Vin), PORT
1, 2 and 3 are tied to one. This operation is achieved asynchronously even if the oscillator does not start-up.
5.8. ALE
Address Latch Enable output for latching the low byte of the address during accesses to external memory. ALE is
activated as though for this purpose at a constant rate of 1/6 the oscillator frequency except during an external data
memory access at which time one ALE pulse is skipped. ALE can sink/source 8 LS TTL inputs. It can drive CMOS
inputs without an external pullup.
5.9. PSEN
Program Store Enable output is the read strobe to external Program Memory. PSEN is activated twice each machine
cycle during fetches from external Program Memory. (However, when executing out of external Program Memory, two
activations of PSEN are skipped during each access to external Data Memory). PSEN is not activated during fetches
from internal Program Memory. PSEN can sink/source 8 LS TTL inputs. It can drive CMOS inputs without an external
pullup.
5.10. EA
When EA is held high, the CPU executes out of internal Program Memory (unless the Program Counter exceeds 1
FFFH). When EA is held low, the CPU executes only out of external Program Memory. EA must not be floated.
5.11. XTAL1
Input to the inverting amplifier that forms the oscillator. Receives the external oscillator signal when an external
oscillator is used.
Output of the inverting amplifier that forms the oscillator. This pin should be floated when an external oscillator is used.
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Rev. I September 18, 1998
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P-80C32 arduino
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80C32/80C52
T2CON (S:C8h)
Timer/Counter 2 Control Register
765
TF2
EXF2
RCLK
4
TCLK
3
EXEN2
2
TR2
1
C/T2#
0
CP/RL2#
Bit
Number
7
Bit
Mnemonic
Description
Timer 2 Overflow flag
TF2
TF2 is not set if RCLK= 1 or TCLK= 1.
Set by hardware when Timer 2 overflows.
Must be cleared by software
Timer 2 External flag
6
EXF2
EXF2 does not cause an interrupt in up/down counter mode (DCEN= 1).
Set by hardware if EXEN2= 1 when a negative transition on T2EX pin is detected.
Receive Clock bit
5
RCLK
Clear to select Timer 1 as the Timer Receive Baud Rate Generator for the Serial Port in modes 1 and 3.
Set to select Timer 2 as the Timer Receive Baud Rate Generator for the Serial Port in modes 1 and 3.
Transmit Clock bit
4
TCLK
Clear to select Timer 1 as the Timer Transmit Baud Rate Generator for the Serial Port in modes 1 and 3.
Set to select Timer 2 as the Timer Transmit Baud Rate Generator for the Serial Port in modes 1 and 3.
Timer 2 External Enable bit
3
EXEN2
Clear to ignore events on T2EX pin for Timer 2.
Set to cause a capture or reload when a negative transition on T2EX pin is detected unless Timer 2 is being
used as the Baud Rate Generator for the Serial Port.
Timer 2 Run Control bit
2 TR2 Clear to turn off Timer 2.
Set to to turn on Timer 2.
Timer 2 Counter/Timer Select bit
1
C/T2#
Clear for Timer operation: Timer 2 counts the divided–down system clock.
Set for Counter operation: Timer 2 counts negative transitions on external pin T2.
Capture/Reload bit
0
CP/RL2#
CP/RL2# is ignored and Timer 2 is forced to auto–reload on Timer 2 overflow if RCLK= 1 or TCLK= 1.
Clear to auto–reload on Timer 2 overflows or negative transitions on T2EX pin if EXEN2= 1.
Set to capture on negative transitions on T2EX pin if EXEN2= 1
Reset Value= 0000 0000b
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Rev. I September 18, 1998
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