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PDF IBM39STB021x Data sheet ( Hoja de datos )
| Número de pieza | IBM39STB021x | |
| Descripción | Digital Set-Top Box Integrated Controllers | |
| Fabricantes | IBM Microelectronics | |
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IBM39STB0210x
Advance
STB0210x Digital Set-Top Box Integrated Controllers
Features
Overall
• IBM Set-Top Box technology
• Four major subsystems integrated with IBM on-
chip CoreConnect™ structure.
• Maximum MIPS for OS and application tasks
• Simplified driver and software development
• Scalable, flexible, and extendible
• 54 MHz/57 MIPS
• 3.3 V and 2.5 V power supplies
• IBM CMOS SA-12E process(0.25 µm)
• 352-pin PBGA package
MPEG-2 Digital Audio/Video Subsystem
• MPEG-2 Video Decoder
• MPEG-2 Audio Decoder
• MPEG-2 Transport/DVB Descrambler
• Macrovision Copy Protection on selected parts
• Display Controller
• Digital Encoder (DENC) with six outputs
• Anti-Flicker Filter
PowerPC 401™ Host Processor: PPC401B3 CPU
• 16KB Instruction, 8KB Data caches
• Universal Interrupt Controller
Memory Subsystem
• DMA Controller
• Cross-Bar Switch
• External Bus Interface Unit (EBIU)
• IDE Interface
• One SDRAM Controller
Peripheral Subsystem
• General Purpose Timers (GPTs)
• Pulse Width Modulators
• Smart Card controller
• I2C Interface
• 16550 Serial Communications Port
• Infrared Serial Communications Port
• General Purpose Inputs/Outputs
• Serial Controller Port
• Modem Serial Interface/Digital Audio Input
Description
IBM STB0210x Digital Set-Top Box Integrated Con-
troller family are highly integrated silicon devices
specifically developed for digital set-top box (STB)
applications using industry-leading IBM CMOS SA-
12E (0.25 µm) process technology.
The STB0210x is part of the second generation of
IBM products for digital STB applications. PowerPC
processing and peripheral I/O architecture provide a
high level of performance and functionality when
used in audio and video subsystems. The resulting
STB technology is full-functioned and easy to use.
The STB0210x minimizes host processor interven-
tion to maximize MIPS for operating system and
application tasks. Most of the features required in
the back end of typical midrange and high-end
STBs are integrated. Driver and software develop-
ment is facilitated while preserving scaleability, flex-
ibility, and extendibility.
Architecturally, the devices consist of four sub-
systems interconnected and tuned using CoreCon-
nect, the IBM multiple-bus, on-chip interconnect
structure:
1. PowerPC host processor
2. Digital audio/video
3. Memory interface
4. Peripheral
These high performance subsystems are suited for
interactive STBs with demanding software require-
ments.
STB02_sds_0327.fm.01
March 27, 2000
www.DataSheet4U.com
Features
Page 1 of 39
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Advance
IBM39STB0210x
STB0210x Digital Set-Top Box Integrated Controllers
PowerPC 401B3 Host Processor Subsystem
The PowerPC 401B3 (PPC401B3) subsystem handles all system initialization and control and also provides
power and flexibility for product differentiation.
PPC401B3 Subsystem
UIC
Interrupts
16KB
I-cache
Array
PPC401B3 Processor
CPU
Interrupt Controller Interface
Timers: PIT, FIT, 64-bit base
Multiplier/Divider
RISC Execution Unit
Core Clocking
Thirty-two 32-bit GPRs
MMU
Instruction
Cache
Controls
Data
Cache
Controls
Interfaces
Clocks
Power Mgmt
DCRs
JTAG (See Note)
8KB
D-cache
Array
PLB Master
PLB Master
Note: The JTAG interface is used for development.
PowerPC 401B3 CPU
The PPC401B3 provides high performance and low power consumption. The CPU executes at sustained
speeds of greater than one cycle per instruction at 54 MHz. Interrupt latency is three cycles, the best time for
critical interrupts.
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Architecture and Subsystem Information
Page 5 of 39
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Advance
IBM39STB0210x
STB0210x Digital Set-Top Box Integrated Controllers
• Uses a locatable Audio Temporary Data and Decoded Audio Data Bank region (programmable base reg-
ister with 128-byte location granularity with additional offset register).
• Includes 256x and 512x DAC sampling clock frequency configurations.
• Has a programmable stream ID register with corresponding 8-bit enable field.
• Provides three PCM output formats in 16- or 20-bit precision:
- I2S
- Left-justified
- Right-justified
• Performs audio bitstream error concealment, either by frame repeats or muting, due to loss of synchroni-
zation or detection of CRC errors.
• Performs MPEG error checking using frame size calculation for each frame.
• Provides a programmable interface that supports the following:
- Play, stop, and mute
- Rate buffer purge to support channel and mode changes
- Provides compressed buffer empty/full indicators
- Synchronization enable/disable for PTS-STC comparison
- Provides buffer fullness value
• Includes SPDIF meeting IEC61937 specs.
• Supports enhanced IEC61937 S/P DIF Channel Status bit by including 16 SPDIF Channel Status bits,
with host control over most of the bits.
• Inserts host-controlled validity bit into SPDIF sub-frame via DCR register.
• Performs audio attenuation in 64 steps, with smooth transitions between steps.
• Provides tone generation with up to 128 generated tones at 31 different durations with seven levels of
attenuation via processor command.
• Supports automated channel change.
• Supports automated time base change.
NTSC/PAL Digital Encoder Unit with Macrovision Copy Protection1
The multi-standard Digital Encoder converts digital audio/video data into analog National Television System
Committee (NTSC) or Phase Alternate Line (PAL) data output formats (see Macrovision Licensing on page
3). It provides up to six concurrent analog video outputs, including S-Video, composite video, YPbPr, and
RGB. The encoder is compatible with SCART connectors, with support for Macrovision Copy Protection Revi-
sion 7. Analog outputs are driven by 10-bit D/A converters, operating at 27 MHz. The outputs drive standard
video levels into 75-Ω loads. It supports closed caption, teletext insertion, and Line 23 WSS (Wide-screen
Signaling) per ITU-R BT.1119. There is a switchable pedestal with gain compensation. Playback of synchro-
nized video data can be locked to the incoming composite video stream.
1. This feature is available only on STB02101, Macrovision license required.
STB02_sds_0327.fm.01
March 27, 2000
Architecture and Subsystem Information
Page 11 of 39
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