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Número de pieza IBM39STB032xx
Descripción (IBM39STB032xx / IBM39STB034xx) Digital Set-Top Box Integrated Controllers
Fabricantes IBM Microelectronics 
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IBM39STB032xx
IBM39STB034xx
Preliminary STB032xx and STB034xx Digital Set-Top Box Integrated Controllers
Features
Overall
• High-End Set-Top Box technology
• Four major subsystems integrated with IBM®
on-chip CoreConnectstructure.
• Maximum MIPS for OS and application tasks
• Simplified driver and software development
• Scalable, flexible, and extendible
• 108 MHz/150 MIPS and 162 MHz/225 MIPS
versions available
• 3.3 V and 2.5 V power supplies
• IBM CMOS SA-12E (0.25 µm) process
technology
• 304-pin PBGA package
MPEG-2 Digital Audio/Video Subsystem
• MPEG-2 Video Decoder
• MPEG-2 Audio Decoder
• MPEG-2 Transport/DVB Descrambler
• Dolby® Digital Audio1 support on selected parts
• Macrovision Copy Protection on selected parts
• Display Controller
• Digital Encoder (DENC) with six outputs
• Anti-Flicker Filter
PowerPC 405Host Processor: PPC405B3 CPU
• 16KB Instruction, 8KB Data caches
• Universal Interrupt Controller
Memory Subsystem
• DMA Controller
• Cross-Bar Switch
• External Bus Interface Unit (EBIU)
• IDE interface
• Two SDRAM Controllers
Peripheral Subsystem
• General Purpose Timers (GPTs)
• Pulse Width Modulators
• 1284 Parallel Port
• Two Smart Card controllers
• Two I2C Interfaces
• 16550 Serial Communications Port
• Infrared Serial Communications Port
• General Purpose Input/Output (GPIO)
• Serial Controller Port
• Modem Serial Interface/Digital Audio Input
Description
IBM STB03xxx Digital Set-Top Box Integrated Con-
troller family are highly integrated silicon devices
specifically developed for digital set-top box (STB)
applications using industry-leading IBM CMOS SA-
12E (0.25 µm) process technology.
The STB03xxx is part of the second generation of
IBM products for digital STB applications. PowerPC
processing and peripheral I/O architecture provide a
high level of performance and functionality when
used in audio and video subsystems. The resulting
STB technology is full-functioned and easy to use.
The STB03xxx minimizes host processor interven-
tion to maximize MIPS for operating system and
application tasks. Most of the features required in
the back end of typical midrange and high-end
STBs are integrated. Driver and software develop-
ment is facilitated while preserving scaleability, flex-
ibility, and extendibility.
Architecturally, the devices consist of four sub-
systems interconnected and tuned using CoreCon-
nect, the IBM multiple-bus, on-chip interconnect
structure:
1. PowerPC host processor
2. Digital audio/video
3. Memory interface
4. Peripheral
These high performance subsystems are suited to
advanced interactive STBs with demanding soft-
ware requirements including web browsers and
Java.
1. This implementation has not yet completed the evaluation
process by Dolby Laboratories and is offered subject to
obtaining approval. A Dolby Digital Audio license is required
from Dolby Laboratories.
STB03_sds_0323.fm.00
March 23, 2000
www.DataSheet4U.com
Features
Page 1 of 54

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IBM39STB032xx pdf
Preliminary
IBM39STB032xx
IBM39STB034xx
STB032xx and STB034xx Digital Set-Top Box Integrated Controllers
PowerPC 405B3 Host Processor Subsystem
The PowerPC 405B3 (PPC405B3) subsystem handles all system initialization and control and also provides
power and flexibility for product differentiation.
PPC405B3 Subsystem
UIC
Interrupts
16KB
I-cache
Array
PPC405B3 Processor
CPU
Interrupt Controller Interface
Timers: PIT, FIT, 64-bit base
Multiplier/Divider
RISC Execution Unit
Core Clocking
Thirty-two 32-bit GPRs
MMU
Instruction
Cache
Controls
Data
Cache
Controls
Interfaces
Clocks
Power Mgmt
DCRs
JTAG (See Note)
8KB
D-cache
Array
PLB Master
PLB Master
Note: The JTAG interface is used for development.
PowerPC 405B3 CPU
The PPC405B3 provides high performance and low power consumption. The CPU executes at sustained
speeds of greater than one cycle per instruction at 108 or 162 MHz. Interrupt latency is three cycles, the best
time for critical interrupts.
STB03_sds_0323.fm.00
March 23, 2000
Architecture and Subsystem Information
Page 5 of 54

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IBM39STB032xx arduino
Preliminary
IBM39STB032xx
IBM39STB034xx
STB032xx and STB034xx Digital Set-Top Box Integrated Controllers
• Performs MPEG-1 and MPEG-2 PES audio parsing, and also accepts audio elementary streams. Parses
and stores ancillary data into external memory for later use by the host processor.
• Supports 16-kHz, 22.05-kHz, 24-kHz, 32-kHz, 44.1-kHz, and 48-kHz audio sampling frequencies.
• Supports audio/video synchronization through PTS/STC comparison with each audio frame.
• Supports Karaoke Mode for Dolby Digital and PCM playback.
• Supports an encoded audio bit rate up to 640 Kbps. This bit rate only pertains to encoded bitstream data.
• Includes Audio Clip Mode for PES, ES, and PCM formats with byte address granularity and 2MB maxi-
mum per clip buffer.
• Allows PCM Mixing with primary audio stream input including sample rate conversion. PCM audio data
supplied via secondary clip mode feature.
• Supports expandable rate buffer size selectable from 4K to 64K (in 4K increments).
• Uses a re-locatable rate buffer region, with a programmable base register (128-byte location granularity).
• Has a re-locatable PTS Value and Ancillary data region, using a programmable base register with 128-
byte location granularity.
• Uses a locatable Audio Temporary Data and Decoded Audio Data Bank region (programmable base reg-
ister with 128-byte location granularity with additional offset register).
• Includes 256x and 512x DAC sampling clock frequency configurations.
• Has a programmable stream ID register with corresponding 8-bit enable field.
• Provides three PCM output formats in 16- or 20-bit precision:
- I2S
- Left-justified
- Right-justified
• Performs audio bitstream error concealment, either by frame repeats or muting, due to loss of synchroni-
zation or detection of CRC errors.
• Performs MPEG error checking using frame size calculation for each frame.
• Provides de-emphasis pins that interface to external de-emphasis circuitry.
• Provides Dolby Surround Mode (dsurmod) pins that interface to external surround mode circuitry.
• Provides a programmable interface that supports the following:
- Play, stop, and mute
- Rate buffer purge to support channel and mode changes
- Provides a compressed buffer full indicator
- Synchronization enable/disable for PTS-STC comparison
• Includes SPDIF meeting IEC61937 and IEC60958 specs.
• Supports enhanced IEC61937 S/P DIF Channel Status bit by including 16 SPDIF Channel Status bits,
with host control over most of the bits.
• Inserts host-controlled validity bit into SPDIF sub-frame via DCR register.
STB03_sds_0323.fm.00
March 23, 2000
Architecture and Subsystem Information
Page 11 of 54

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