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PDF DPS9245 Data sheet ( Hoja de datos )
| Número de pieza | DPS9245 | |
| Descripción | High-resolution ADC With Pga Datasheet 11/00 | |
| Fabricantes | LSI Logic Corporation | |
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DPS9245
High-Resolution ADC
with PGA
Datasheet
The DPS9245 is a versatile, analog front end that combines a high-
resolution 5 megasamples per second (MS/s) 16-bit Analog-to-Digital
Converter (ADC), a built-in reference, and a Programmable Gain
Amplifier (PGA) with resistive input impedance in a 44-pin package.
Figure 1
DPS9245 Block Diagram
RESETB
REFCLK
Differential
Analog In
(INP, INM)
Low-Noise PGA
(7 Settings)
S/H and
ADC
16
OVR_RNG
Data
AD[15:0]
OE
GAIN[2:0]
VREF
The chip includes a digitally-calibrated, pipeline ADC that is calibrated
upon assertion of a simple reset signal. The combination of a low-noise,
high-linearity, high-input impedance buffer (with programmable gain),
wideband S/H, on-board voltage references, and simple digital interface
(16-bit parallel output word synchronous with the master sampling clock),
makes the chip extremely easy to use in a wide variety of systems. The
analog inputs should be driven differentially, and can be AC-coupled or
DC-coupled to a source. Typical applications include high-performance
data acquisition systems, automatic test equipment, and wideband digital
communications receivers present in systems such as wireless
basestations. The performance of the device with respect to linearity and
noise should be considered separately, as indicated by the THD and
SNR specifications provided in this document.
November 2000
Copyright © 1999, 2000 by LSI Logic Corporation. All rights reserved.
www.DataSheet4U.com
1
1 page  
Table 2
Digital I/O DC Electrical Characteristics
Parameter
Min Typ Max Units Notes/Conditions
VOH (High-level output voltage) VDD-0.5
–
–
V At IOH = −2 mA
VOL (Low-level output voltage)
–
– 0.5
V At IOL = 2 mA
IIL (Input leakage current)
−10 – +10 µA
VIH (High-level input voltage) 2.4 – – V
VIL (Low-level input voltage)
– – 0.8 V
Note:
For all digital outputs, the VOH specification of VDD-0.5V
refers to the VDD_ADIO supply (pin 6). The exception is
the BUSYB output (pin 33), whose output HIGH level is ref-
erenced to the VDDD_ADC power supply (pins 3, 4).
Dynamic Linearity Specifications for Sinusoidal Differential Analog
(SDA) Input
Table 3 provides the dynamic linearity specifications for SDA input. The
conditions are:
• VDD_ADC = VDDD_ADC = 5.0 V
• VDD_ADIO = 3.3 V
• REXT = 1.43 kΩ.
The following notes apply:
1. The signal level relative to full-scale (dBFS) is given at the ADC input
– that is, after the PGA – in order to show the dependence on PGA
gain.
2. 0 dBFS is 5.0V peak-to-peak differential.
3. Second harmonic distortion (HD2), 3rd harmonic distortion (HD3),
total harmonic distortion up to and including the 9th harmonic
(THD_9), and spurious free dynamic range (SFDR), are given in dB
below the fundamental (carrier).
DPS9245 High-Resolution ADC with PGA
5
5 Page 
IC Operation and Functionality
The following sections describe in greater detail the individual blocks and
functions of the DPS9245:
• Overview
• Chip Startup/Initialization Sequence
• Analog Input Interfacing
• External Connections
• ADC Digital Output Timing
• ADC References
• Other ADC Functions
• Programmable Gain Amplifier
Overview
The incoming analog differential signal (maximum level 5 V peak-to-peak
differential) enters the chip at the INP/INM pins. The analog signal path
is partitioned into a programmable gain amplifier (PGA) and an ADC. The
PGA has maximum gain of +20 dB; the gain is set by the digital control
signals GAIN[2:0]. The output of the PGA is fed directly to the ADC,
which samples at a rate equal to the REFCLK frequency and outputs a
16-bit wide parallel word.
The ADC uses a pipeline multistage architecture. Latency is 6 clock
cycles.
The chip requires a single low-jitter clock to be applied at the REFCLK
pin, with nominal 50% duty cycle. All clock generation is performed
internally and all converter and S/H clocks in the ADC path are directly
derived from REFCLK.
Chip Startup/Initialization Sequence
Warning: This initialization sequence is required. Without it, the chip
will not work.
DPS9245 High-Resolution ADC with PGA
11
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