PDF ICS650-36 Data sheet ( Hoja de datos )

Número de pieza	ICS650-36
Descripción	Networking & PCI Clock Source
Fabricantes	Integrated Circuit Systems
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No Preview Available ! ICS650-36 Networking & PCI Clock Source Description The ICS650-36 is a low cost frequency generator designed to support networking and PCI applications. Using analog/digital Phase Locked-Loop (PLL) techniques, the device uses a standard fundamental mode, inexpensive crystal input of 25 MHz to produce four output clocks supporting LAN, PCI, and 100M SDRAM functions. The device also has a power down feature that tri-states the clock outputs and turns off the PLL when the PDTS pin is taken low. Features • Packaged in 16-pin TSSOP • Available in Pb (lead) free package • Replaces multiple crystals and oscillators • Input crystal or clock frequency of 25 MHz • Fixed reference output frequency of 25 MHz • Selectable output frequencies of 33.3, 33.333, 50, 66.666, 100, and 125 MHz • Duty cycle of 40/60 • Operating voltage of 3.3 V • Advanced, low-power CMOS process • Industrial and commercial temperature ranges Block Diagram 3 S2:0 Select/ Control Circuit X1/ICLK 25 MHz crystal input X2 Crystal Oscillator/ Clock Buffer External capacitors may be required. VDD 3 PLL1 PLL2 CLK1 CLK2 PLL3 3 GND CLK3 REF PDTS (all outputs and PLLs) MDS 650-36 D 1 Revision 030206 Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201● www.icst.com 1 page ICS650-36 Networking & PCI Clock Source DC Electrical Characteristics Unless stated otherwise, VDD = 3.3 V ±5%, Ambient Temperature -40 to +85°C Parameter Symbol Conditions Min. Typ. Operating Voltage VDD 3.135 3.3 Supply Current IDD No load, PDTS=1 25 Power Down Current IDDPD No load, PDTS=0 100 Input High Voltage Input Low Voltage Output High Voltage Output High Voltage Output Low Voltage Short Circuit Current Input Capacitance, inputs Nominal Output Impedance Internal Pull-up Resistor Internal Pull-down Resistor VIH VIL VOH VOH VOL IOS CIN ZOUT RPU RPD PDTS, S2:0 PDTS, S2:0 IOH = -4 mA IOH = -12 mA IOL = 12 mA Clock outputs PDTS, S2:0 Outputs 2 VDD-0.3 2.4 ±65 5 20 500 250 Max. 3.465 0.8 0.4 Units V mA µA V V V V V mA pF Ω kΩ kΩ AC Electrical Characteristics Unless stated otherwise, VDD = 3.3 V ±5%, Ambient Temperature -40 to +85°C Parameter Symbol Conditions Min. Typ. Input Frequency Output Rise Time Output Fall Time Output Clock Duty Cycle fIN tOR 20% to 80%, Note 1 tOF 80% to 20%, Note 1 at VDD/2, Note 1 40 25 0.8 0.7 Absolute Clock Period Jitter Note 1 ±125 Clock Jitter, Cycle-to-Cycle 33.333M, 66.666M, Note 1 150 Clock Jitter, Long Term 25M, n=1000, Note1 900 Frequency Synthesis Error 0 Output Enable Time tOE PDTS high to output locked to ±1% 350 Output Disable Time tOD PDTS low to tri-state 25 Note 1: Measured with a 15 pF load. Max. Units MHz ns ns 60 % ps ps ps ppm µs ns MDS 650-36 D 5 Revision 030206 Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201● www.icst.com 5 Page

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Número de pieza	Descripción	Fabricantes
ICS650-36	Networking & PCI Clock Source	Integrated Circuit Systems

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