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Número de pieza | ICS650R-27 | |
Descripción | Networking Clock Source | |
Fabricantes | Integrated Circuit Systems | |
Logotipo | ||
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No Preview Available ! ICS650-27
Networking Clock Source
Description
The ICS650-27 is a low cost, low jitter, high
performance clock synthesizer for networking
applications. Using analog Phase-Locked Loop (PLL)
techniques, the device accepts a 12.5 MHz or 25 MHz
clock or fundamental mode crystal input to produce
multiple output clocks for networking chips, PCI
devices, SDRAM, and ASICs. The ICS650-27 outputs
all have zero ppm synthesis error.
The ICS650-27 is pin compatible and functionally
equivalent to the ICS650-07. It is a performance
upgrade and is recommended for all new 3.3V
designs.
See the MK74CB214, ICS551, and ICS552-01 for
non-PLL buffer devices which produce multiple
low-skew copies of these output clocks.
See the ICS570, ICS9112-16/17/18 for zero delay
buffers that can synchronize outputs and other needed
clocks.
Features
• Packaged in 20-pin (150 mil) SSOP (QSOP)
• Available in Pb (lead) free package
• 12.5 MHz or 25 MHz fundamental crystal or clock
input
• Six output clocks with selectable frequencies
• SDRAM frequencies of 67, 83, 100, and 133 MHz
• Buffered crystal reference output
• Zero ppm synthesis error in all clocks
• Ideal for PMC-Sierra’s ATM switch chips
• Full CMOS output swing with 25 mA output drive
capability at TTL levels
• Advanced, low-power, sub-micron CMOS process
• Operating voltage of 3.3 V
• Industrial temperature only
Block Diagram
ACS1:0
BCS1:0
CCS
2
2
25 or 12.5 MHz
cyrstal or clock
X1/ICLK
X2
VDD
2
Clock
Buffer/
Crystal
Oscillator
Clock
Synthesis
and Control
Circuitry
2
GND
CLKA1
/2 CLKA2
CLKB1
/2 CLKB2
CLKC1
CLKC2
REFOUT
OE (all outputs)
MDS 650-27 D
1
Revision 070505
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
1 page ICS650-27
Networking Clock Source
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V ±10%, Ambient Temperature -40 to +85°C
Parameter
Symbol
Conditions
Min.
Operating Voltage
VDD
3.0
Input High Voltage
Input Low Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage, CMOS level
Operating Supply Current
Short Circuit Current
Internal pull-up resistor
VIH X1 pin only, CLK input
VIL X1 pin only, CLK input
VIH all tri-level type inputs
VIL all tri-level type inputs
VIH all other inputs
VIL all other inputs
VOH IOH = -25 mA
VOL IOL = 25mA
VOH IOH = -8 mA
IDD No Load
IOS Each output
RPU BCS1, OE pins
ACSI pin
VDD/2+1
VDD-0.5
2
2.4
VDD-0.4
Nominal output impedance
ZOUT
Typ.
3.3
VDD/2
VDD/2
50
±50
510
120
20
Max.
3.6
VDD/2-1
0.5
0.8
0.8
Units
V
V
V
V
V
V
V
V
V
V
mA
mA
kΩ
kΩ
Ω
AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V±10%, Ambient Temperature -40 to +85°C
Parameter
Symbol
Conditions
Min.
Input Frequency
10
Output Rise Time
Output Fall Time
Output Clock Duty Cycle
Frequency Error
Absolute Jitter, short term
Note 1: Measured with 15 pF load
tOR 0.8 to 2.0 V, Note 1
tOF 2.0 to 0.8 V, Note 1
At VDD/2, Note 1
All clocks
Variation from mean,
Note 1
40
Typ. Max. Units
12.5 or 27
25
MHz
1.5 ns
1.5 ns
50 60 %
0 ppm
±150
ps
Thermal Characteristics
Parameter
Thermal Resistance Junction to Ambient
Thermal Resistance Junction to Case
Symbol Conditions
θJA Still air
θJA 1 m/s air flow
θJA 3 m/s air flow
θJC
Min.
Typ.
135
93
78
60
Max. Units
°C/W
°C/W
°C/W
°C/W
MDS 650-27 D
5
Revision 070505
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
5 Page |
Páginas | Total 6 Páginas | |
PDF Descargar | [ Datasheet ICS650R-27.PDF ] |
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