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PDF ICS650-07C Data sheet ( Hoja de datos )
| Número de pieza | ICS650-07C | |
| Descripción | Networking Clock Source | |
| Fabricantes | Integrated Circuit Systems | |
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( DataSheet : www.DataSheet4U.com )
PRELIMINARY INFORMATION
ICS650-07C
Networking Clock Source
Description
The ICS650-07C is a low cost, low jitter, high
performance clock synthesizer for networking
applications. Using analog Phase-Locked Loop
(PLL) techniques, the device accepts a 12.5 MHz
or 25.00 MHz clock or fundamental mode crystal
input to produce multiple output clocks for
networking chips, PCI devices, SDRAM, and
ASICs. The ICS650-07C outputs all have 0 ppm
synthesis error.
See the MK74CB214, ICS551, and ICS552-01 for
non-PLL buffer devices which produce multiple
low-skew copies of these output clocks.
See the ICS570, ICS9112-16/17/18 for zero delay
buffers that can synchronize outputs and other
needed clocks.
Features
• Packaged in 20 pin narrow (150 mil) SSOP (QSOP)
• 12.5 MHz or 25.00 MHz fundamental crystal or
clock input
• Six output clocks with selectable frequencies
• SDRAM frequencies of 67, 83, 100, and 133 MHz
• Buffered crystal reference output
• Zero ppm synthesis error in all clocks
• Ideal for PMC-Sierra’s ATM switch chips
• Full CMOS output swing with 25 mA output drive
capability at TTL levels
• Advanced, low power, sub-micron CMOS process
• 3.0V to 5.5V operating voltage
Block Diagram
VDD GND
22
2
Output
Buffer
CLKA1
ACS1,0
÷2
Output
Buffer
CLKA2
BCS1,0
2
Clock Synthesis
and Control
Circuitry
Output
Buffer
CLKB1
CCS
÷2
Output
Buffer
CLKB2
12.5 MHz or
25.00 MHz
crystal or clock
X1
X2
Clock
Buffer/
Crystal
Oscillator
Output
Buffer
Output
Buffer
Output
Buffer
CLKC1
CLKC2
REFOUT
OE (all outputs)
Optional crystal capacitors are shown and may be required for tuning of initial accuracy (determined once per board).
MDS 650-07C A
1
Revision 101399
Printed 11/28/00
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126•(408)295-9800tel • www.icst.com
www.DataSheet4U.com
1 page  
PRELIMINARY INFORMATION
ICS650-07C
Networking Clock Source
Package Outline and Package Dimensions
(For current dimensional specifications, see JEDEC Publication No. 95.)
INDEX
AREA
1
2
D
E1 E
20 pin SSOP
Symbol
A
A1
b
c
D
e
E
E1
L
Inches
Min Max
0.053 0.069
0.004 0.010
0.008 0.012
0.007 0.010
0.337 0.344
.025 BSC
0.228 0.244
0.150 0.157
0.016 0.050
Millimeters
Min Max
1.35 1.75
0.10 0.25
0.20 0.30
0.19 0.25
8.56 8.74
0.635 BSC
5.79 6.20
3.81 3.99
0.41 1.27
A1
e
c
b
A
L
Ordering Information
Part/Order Number
ICS650R-07
ICS650R-07T
ICS650R-07I
ICS650R-07IT
Marking
ICS650R-07
ICS650R-07
ICS650R-07I
ICS650R-07I
Shipping packaging
tubes
tape and reel
tubes
tape and reel
Note: The C on the data sheet (ICS650-07C) is not significant when ordering this chip.
Package
20 pin SSOP
20 pin SSOP
20 pin SSOP
20 pin SSOP
Temperature
0-70°C
0-70°C
-40 to +85°C
-40 to +85°C
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Inc (ICS) assumes no responsibility for either its use or for
the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental
requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize
or warrant any ICS product for use in life support devices or critical medical instruments.
MDS 650-07C A
5
Revision 101399
Printed 11/28/00
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126•(408)295-9800tel • www.icst.com
5 Page | ||
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| PDF Descargar | [ Datasheet ICS650-07C.PDF ] | |
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