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PDF SDA3526-5 Data sheet ( Hoja de datos )
| Número de pieza | SDA3526-5 | |
| Descripción | Nonvolatile Memory 2K-Bit EPROM | |
| Fabricantes | Siemens | |
| Logotipo |  |
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Nonvolatile Memory 2-Kbit E2PROM
with I2C Bus and 2 K Write Protection
SDA 3526-5
Preliminary Data
MOS IC
Features
q Word-organized programmable nonvolatile memory in
n-channel floating-gate technology (E2PROM)
q 256 × 8-bit organization
q Supply voltage 5 V
q Serial 2-line bus for data input and output (I2C Bus)
q Reprogramming mode, 10 ms erase / write cycle
q Reprogramming by means of on-chip control (without
external control)
q Check for end of programming process
q Programming protect mode
q Data retention > 10 years
q More than 104 reprogramming cycles per address
P-DIP-8-1
Type
SDA 3526-5
Ordering Code
Q67100-H5099
Package
P-DIP-8-1
Circuit Description
I2C Bus Interface
The I2C Bus is a bidirectional 2-line bus for the transfer of data between various integrated circuits.
It consists of a serial data line SDA and a serial clock line SCL. The data line requires an external
pull-up resistor to VCC (open drain output stage).
The possible operational states of the I2C Bus are shown in figure 1. In the quiescent state, both
lines SDA and SCL are high, i.e. the output stage of the data line is disabled. As long a SCL remains
"1", information changes on the data bus indicate the start or the end of data transfer between two
components.
The transition on SDA from "1" to "0" is a start condition, the transition from "0" to "1" is a stop
condition. During a data transfer the information on the data bus will only change while the clock line
SCL is "0". The information on SDA is valid as long as SCL is "1".
In conjunction with an I2C Bus system, the memory component can operate as a receiver and as a
transmitter (slave receiver or slave transmitter). Between a start and stop condition, information is
always transmitted in byte-organized form. Between the falling edge of the eighth clock pulse and
a ninth acknowledge clock pulse, the memory component sets the SDA-line to low as a confirmation
of reception, if the chip select conditions have been met. During the output of data, the data output
of the memory is high in impedance during the ninth clock pulse (acknowledge master).
The signal timing required for the operation of the I2C Bus is summarized in figure 2.
Semiconductor Group
53
07.94
1 page  
SDA 3526-5
Block Diagram
Semiconductor Group
57
5 Page 
SDA 3526-5
Figure 3
Programming
Control word input
ST CS/E As
WA
As
DE
As
SP
(the reprogramming starts after
this stop condition)
Check for end of programming ST CS/A As
1. when As = 1 programming is not terminated
2. when As = 0 programming is terminated
Abort programming
ST CS/E As
Figure 4
Read
Control word input read
a) complete (with word address input)
ST CS/E As WA As ST CS/A As DA Am DA Am SP
b) shortened:
Bit 0 … 7 the last selected word
address remain unchanged
n bytes
Last byte
Automatic incrementation
of the word address
ST CS/A As DA Am DA Am SP
n bytes
Last byte
Autoincrement
Prior to stop condition
Am = 0
Am = 1
Semiconductor Group
63
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet SDA3526-5.PDF ] | |
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