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PDF C8051F327 Data sheet ( Hoja de datos )

Número de pieza C8051F327
Descripción (C8051F326 / C8051F327) Full Speed USB / 16k ISP FLASH MCU Family
Fabricantes Silicon Laboratories　
Logotipo Silicon Laboratories Logotipo



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C8051F326/7
Full Speed USB, 16 kB Flash MCU Family
USB Function Controller
- USB specification 2.0 compliant
- Full speed (12 Mbps) or low speed (1.5 Mbps)
operation
- Integrated clock recovery; no external crystal
required for full speed or low speed
- Supports three fixed-function endpoints
- 256 Byte USB buffer memory
- Integrated transceiver; no external resistors
required
On-Chip Debug
- On-chip debug circuitry facilitates full speed,
non-intrusive in-system debug (no emulator
required)
- Provides breakpoints, single stepping,
inspect/modify memory and registers
- Superior performance to emulation systems using
ICE-chips, target pods, and sockets
Voltage Supply Input: 2.7 to 5.25 V
- Voltages from 3.6 to 5.25 V supported using
On-Chip Voltage Regulator
High Speed 8051 µC Core
- Pipelined instruction architecture; executes 70% of
instructions in 1 or 2 system clocks
- Up to 25 MIPS throughput with 25 MHz clock
- Expanded interrupt handler
Memory
- 1536 bytes internal RAM
(1 k + 256 + 256 USB FIFO)
- 16k bytes Flash; In-system programmable in
512-byte sectors
Digital Peripherals
- 15 Port I/O; All 5 V tolerant with high sink current
- Enhanced UART
- Two general purpose 16-bit timers
Clock Sources
- Internal oscillator: 0.25% accuracy with clock
recovery enabled. Supports all USB and UART
modes
- External CMOS clock
- Can switch between clock sources on-the-fly; useful
in power saving strategies
Packages
- 28-pin QFN
- Temperature Range: –40 to +85 °C
ANALOG
PERIPHERALS
VREG
DIGITAL I/O
UART
Timer 0
Timer 1
Port 0
Port 2
Port 3
USB Controller / Transceiver
PRECISION INTERNAL
OSCILLATOR
LOW FREQUENCY
OSCILLATOR
HIGH-SPEED CONTROLLER CORE
16 KB
ISP FLASH
8
INTERRUPTS
8051 CPU
(25MIPS)
DEBUG
CIRCUITRY
1536 B
SRAM
POR
Rev. 0.5 1/06
Copyright © 2006 by Silicon Laboratories
C8051F326/7
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.

1 page




C8051F327 pdf
C8051F326/7
12.12.2.Endpoint1 IN Isochronous Mode.......................................................... 110
12.13.Controlling Endpoint1 OUT........................................................................... 114
12.13.1.Endpoint1 OUT Interrupt or Bulk Mode................................................ 114
12.13.2.Endpoint1 OUT Isochronous Mode...................................................... 114
13. UART0.................................................................................................................... 119
13.1.Baud Rate Generator ..................................................................................... 120
13.2.Data Format.................................................................................................... 122
13.3.Configuration and Operation .......................................................................... 123
13.3.1.Data Transmission ................................................................................. 123
13.3.2.Data Reception ...................................................................................... 123
13.3.3.Multiprocessor Communications ............................................................ 124
14. Timers ................................................................................................................... 129
14.1.Timer 0 and Timer 1 Operating Modes........................................................... 129
14.1.1.Mode 0: 13-bit Timer .............................................................................. 130
14.1.2.Mode 1: 16-bit Timer .............................................................................. 131
14.1.3.Mode 2: 8-bit Timer with Auto-Reload.................................................... 131
14.1.4.Mode 3: Two 8-bit Timers (Timer 0 Only) .............................................. 132
15. C2 Interface ........................................................................................................... 137
15.1.C2 Interface Registers.................................................................................... 137
15.2.C2 Pin Sharing ............................................................................................... 139
Contact Information.................................................................................................. 140
Rev. 0.5
5

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C8051F327 arduino
C8051F326/7
List of Registers
SFR Definition 5.1. REG0CN: Voltage Regulator Control . . . . . . . . . . . . . . . . . . . . . . 36
SFR Definition 6.1. DPL: Data Pointer Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
SFR Definition 6.2. DPH: Data Pointer High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
SFR Definition 6.3. SP: Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
SFR Definition 6.4. PSW: Program Status Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
SFR Definition 6.5. ACC: Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
SFR Definition 6.6. B: B Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
SFR Definition 6.7. IE: Interrupt Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
SFR Definition 6.8. IP: Interrupt Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
SFR Definition 6.9. EIE1: Extended Interrupt Enable 1 . . . . . . . . . . . . . . . . . . . . . . . . 55
SFR Definition 6.10. EIP1: Extended Interrupt Priority 1 . . . . . . . . . . . . . . . . . . . . . . . 55
SFR Definition 6.11. EIE2: Extended Interrupt Enable 2 . . . . . . . . . . . . . . . . . . . . . . . 55
SFR Definition 6.12. EIP2: Extended Interrupt Priority 2 . . . . . . . . . . . . . . . . . . . . . . . 56
SFR Definition 6.13. PCON: Power Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
SFR Definition 7.1. VDM0CN: VDD Monitor Control . . . . . . . . . . . . . . . . . . . . . . . . . . 61
SFR Definition 7.2. RSTSRC: Reset Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
SFR Definition 8.1. PSCTL: Program Store R/W Control . . . . . . . . . . . . . . . . . . . . . . . 68
SFR Definition 8.2. FLKEY: Flash Lock and Key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
SFR Definition 8.3. FLSCL: Flash Scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
SFR Definition 9.1. EMI0CN: External Memory Interface Control . . . . . . . . . . . . . . . . 72
SFR Definition 10.1. OSCICN: Internal Oscillator Control . . . . . . . . . . . . . . . . . . . . . . 74
SFR Definition 10.2. OSCICL: Internal Oscillator Calibration . . . . . . . . . . . . . . . . . . . . 75
SFR Definition 10.3. OSCLCN: Internal L-F Oscillator Control . . . . . . . . . . . . . . . . . . . 76
SFR Definition 10.4. CLKMUL: Clock Multiplier Control . . . . . . . . . . . . . . . . . . . . . . . . 77
SFR Definition 10.5. CLKSEL: Clock Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
SFR Definition 11.1. GPIOCN: Global Port I/O Control . . . . . . . . . . . . . . . . . . . . . . . . 84
SFR Definition 11.2. P0: Port0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
SFR Definition 11.3. P0MDOUT: Port0 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 84
SFR Definition 11.4. P2: Port2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
SFR Definition 11.5. P2MDOUT: Port2 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 85
SFR Definition 11.6. P3: Port3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
SFR Definition 11.7. P3MDOUT: Port3 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 86
USB Register Definition 12.1. USB0XCN: USB0 Transceiver Control . . . . . . . . . . . . . 91
USB Register Definition 12.2. USB0ADR: USB0 Indirect Address . . . . . . . . . . . . . . . . 93
USB Register Definition 12.3. USB0DAT: USB0 Data . . . . . . . . . . . . . . . . . . . . . . . . . 94
USB Register Definition 12.4. INDEX: USB0 Endpoint Index . . . . . . . . . . . . . . . . . . . . 94
USB Register Definition 12.5. CLKREC: Clock Recovery Control . . . . . . . . . . . . . . . . 96
USB Register Definition 12.6. FIFOn: USB0 Endpoint FIFO Access . . . . . . . . . . . . . . 98
USB Register Definition 12.7. FADDR: USB0 Function Address . . . . . . . . . . . . . . . . . 99
USB Register Definition 12.8. POWER: USB0 Power . . . . . . . . . . . . . . . . . . . . . . . . 101
USB Register Definition 12.9. FRAMEL: USB0 Frame Number Low . . . . . . . . . . . . . 102
USB Register Definition 12.10. FRAMEH: USB0 Frame Number High . . . . . . . . . . . 102
USB Register Definition 12.11. IN1INT: USB0 IN Endpoint Interrupt . . . . . . . . . . . . . 103
Rev. 0.5
11

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