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PDF C8051F321 Data sheet ( Hoja de datos )

Número de pieza C8051F321
Descripción (C8051F320 / C8051F321) Full Speed USB / 16k ISP FLASH MCU Family
Fabricantes Cygnal Integrated Products 
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No Preview Available ! C8051F321 Hoja de datos, Descripción, Manual

( DataSheet : www.DataSheet4U.com )
Preliminary
C8051F320/1
Full Speed USB, 16K ISP FLASH MCU Family
ANALOG PERIPHERALS
- 10-Bit ADC
Up to 200 ksps
Up to 17 or 13 External Single-Ended or Differential
Inputs
VREF from External Pin, Internal Reference, or VDD
Built-in Temperature Sensor
External Conversion Start Input
- Two Comparators
- Internal Voltage Reference
- POR/Brown-Out Detector
USB FUNCTION CONTROLLER
- USB Specification 2.0 Compliant
- Full Speed (12 Mbps) or Low Speed (1.5 Mbps)
Operation
- Integrated Clock Recovery; No External Crystal
Required for Full Speed or Low Speed
- Supports Eight Flexible Endpoints
- 1k Byte USB Buffer Memory
- Integrated Transceiver; No External Resistors Required
ON-CHIP DEBUG
- On-Chip Debug Circuitry Facilitates Full Speed,
Non-Intrusive In-System Debug (No Emulator
Required!)
- Provides Breakpoints, Single Stepping,
Inspect/Modify Memory and Registers
- Superior Performance to Emulation Systems Using
ICE-Chips, Target Pods, and Sockets
VOLTAGE REGULATOR INPUT: 4.0V TO 5.25V
HIGH SPEED 8051 µC Core
- Pipelined Instruction Architecture; Executes 70% of
Instructions in 1 or 2 System Clocks
- Up to 25 MIPS Throughput with 25 MHz Clock
- Expanded Interrupt Handler
MEMORY
- 2304 Bytes Internal RAM (1k + 256 + 1k USB FIFO)
- 16k Bytes FLASH; In-system programmable in 512-byte
Sectors
DIGITAL PERIPHERALS
- 25/21 Port I/O; All 5 V tolerant with High Sink Current
- Hardware Enhanced SPI™, Enhanced UART, and
SMBus™ Serial Ports
- Four General Purpose 16-Bit Counter/Timers
- 16-Bit Programmable Counter Array (PCA) with Five
Capture/Compare Modules
- Real Time Clock Mode using External Clock Source and
PCA or Timer
CLOCK SOURCES
- Internal Oscillator: 0.25% Accuracy with Clock
Recovery enabled. Supports all USB and UART Modes
- External Oscillator: Crystal, RC, C, or Clock (1 or 2 Pin
Modes)
- Can Switch Between Clock Sources on-the-fly; Useful in
Power Saving Strategies
PACKAGES
- 32-pin LQFP (C8051F320)
- 28-pin MLP (C8051F321)
TEMPERATURE RANGE: -40°C TO +85°C
ANALOG
PERIPHERALS
A 10-bit +
M
U
200ksps -
+
X ADC
-
TEMP
SENSOR
VREF
VREG
DIGITAL I/O
UART
SPI
SMBus
PCA
Timer 0
Timer 1
Timer 2
Timer 3
Port 0
Port 1
Port 2
Port 3
PRECISION INTERNAL
OSCILLATOR
USB Controller /
Transceiver
HIGH-SPEED CONTROLLER CORE
16KB
ISP FLASH
16
INTERRUPTS
8051 CPU
(25MIPS)
DEBUG
CIRCUITRY
2304 B
SRAM
POR WDT
DS010-1.0 APR03
www.DataSheet4U.com
CYGNAL Integrated Products, Inc. © 2003
Page 1
www.DataSheet4U.com

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C8051F321 pdf
Preliminary
C8051F320/1
14.2.Port I/O Initialization.....................................................................................................131
14.3.General Purpose Port I/O...............................................................................................134
15. UNIVERSAL SERIAL BUS CONTROLLER (USB0) ....................................................143
15.1.Endpoint Addressing .....................................................................................................144
15.2.USB Transceiver ...........................................................................................................144
15.3.USB Register Access.....................................................................................................146
15.4.USB Clock Configuration .............................................................................................150
15.5.FIFO Management.........................................................................................................151
15.5.1. FIFO Split Mode ..................................................................................................151
15.5.2. FIFO Double Buffering .......................................................................................151
15.5.3. FIFO Access ........................................................................................................152
15.6.Function Addressing......................................................................................................153
15.7.Function Configuration and Control .............................................................................154
15.8.Interrupts .......................................................................................................................157
15.9.The Serial Interface Engine ...........................................................................................161
15.10.Endpoint0 .....................................................................................................................161
15.10.1.Endpoint0 SETUP Transactions .........................................................................162
15.10.2.Endpoint0 IN Transactions .................................................................................162
15.10.3.Endpoint0 OUT Transactions .............................................................................163
15.11.Configuring Endpoints1-3 ...........................................................................................166
15.12.Controlling Endpoints1-3 IN .......................................................................................166
15.12.1.Endpoints1-3 IN Interrupt or Bulk Mode ...........................................................166
15.12.2.Endpoints1-3 IN Isochronous Mode...................................................................167
15.13.Controlling Endpoints1-3 OUT ...................................................................................170
15.13.1.Endpoints1-3 OUT Interrupt or Bulk Mode .......................................................170
15.13.2.Endpoints1-3 OUT Isochronous Mode...............................................................170
16. SMBUS..................................................................................................................................175
16.1.Supporting Documents ..................................................................................................176
16.2.SMBus Configuration....................................................................................................176
16.3.SMBus Operation ..........................................................................................................177
16.3.1. Arbitration............................................................................................................177
16.3.2. Clock Low Extension...........................................................................................178
16.3.3. SCL Low Timeout ...............................................................................................178
16.3.4. SCL High (SMBus Free) Timeout.......................................................................178
16.4.Using the SMBus...........................................................................................................179
16.4.1. SMBus Configuration Register............................................................................180
16.4.2. SMB0CN Control Register ..................................................................................183
16.4.3. Data Register........................................................................................................186
16.5.SMBus Transfer Modes.................................................................................................187
16.5.1. Master Transmitter Mode ....................................................................................187
16.5.2. Master Receiver Mode.........................................................................................188
16.5.3. Slave Receiver Mode ...........................................................................................189
16.5.4. Slave Transmitter Mode.......................................................................................190
16.6.SMBus Status Decoding................................................................................................191
17. UART0 ..................................................................................................................................193
© 2003 Cygnal Integrated Products, Inc. DS010-1.0 APR03
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C8051F321 arduino
Preliminary
C8051F320/1
Figure 9.14. EIP2: Extended Interrupt Priority 2.....................................................................94
Figure 9.15. IT01CF: INT0/INT1 Configuration Register ......................................................95
Figure 9.16. PCON: Power Control Register ..........................................................................97
10. RESET SOURCES .............................................................................................................99
Figure 10.1. Reset Sources ......................................................................................................99
Figure 10.2. Power-On and VDD Monitor Reset Timing .....................................................100
Figure 10.3. VDM0CN: VDD Monitor Control ....................................................................101
Figure 10.4. RSTSRC: Reset Source Register.......................................................................104
Table 10.1. Reset Electrical Characteristics .........................................................................105
11. FLASH MEMORY ...........................................................................................................107
Table 11.1. FLASH Electrical Characteristics .....................................................................108
Figure 11.1. FLASH Program Memory Map and Security Byte...........................................110
Figure 11.2. PSCTL: Program Store R/W Control ................................................................110
Figure 11.3. FLKEY: FLASH Lock and Key Register .........................................................111
Figure 11.4. FLSCL: FLASH Scale Register ........................................................................111
12. EXTERNAL RAM ............................................................................................................113
Figure 12.1. External Ram Memory Map..............................................................................113
Figure 12.2. XRAM Memory Map Expanded View .............................................................114
Figure 12.3. EMI0CN: External Memory Interface Control .................................................115
13. OSCILLATORS ..................................................................................................................117
Figure 13.1. Oscillator Diagram ............................................................................................117
Figure 13.2. OSCICN: Internal Oscillator Control Register .................................................119
Figure 13.3. OSCICL: Internal Oscillator Calibration Register ............................................119
Figure 13.4. OSCXCN: External Oscillator Control Register...............................................122
Figure 13.5. CLKMUL: Clock Multiplier Control Register..................................................123
Table 13.1. Typical USB Full Speed Clock Settings ...........................................................124
Table 13.2. Typical USB Low Speed Clock Settings...........................................................124
Figure 13.6. CLKSEL: Clock Select Register .......................................................................125
Table 13.3. Internal Oscillator Electrical Characteristics.....................................................126
14. PORT INPUT/OUTPUT ..................................................................................................127
Figure 14.1. Port I/O Functional Block Diagram ..................................................................127
Figure 14.2. Port I/O Cell Block Diagram.............................................................................128
Figure 14.3. Crossbar Priority Decoder with No Pins Skipped .............................................129
Figure 14.4. Crossbar Priority Decoder with Crystal Pins Skipped ......................................130
Figure 14.5. XBR0: Port I/O Crossbar Register 0 .................................................................132
Figure 14.6. XBR1: Port I/O Crossbar Register 1 .................................................................133
Figure 14.7. P0: Port0 Register..............................................................................................135
Figure 14.8. P0MDIN: Port0 Input Mode Register ...............................................................135
Figure 14.9. P0MDOUT: Port0 Output Mode Register.........................................................136
Figure 14.10. P0SKIP: Port0 Skip Register...........................................................................136
Figure 14.11. P1: Port1 Register............................................................................................137
Figure 14.12. P1MDIN: Port1 Input Mode Register .............................................................137
Figure 14.13. P1MDOUT: Port1 Output Mode Register.......................................................138
Figure 14.14. P1SKIP: Port1 Skip Register...........................................................................138
Figure 14.15. P2: Port2 Register............................................................................................139
© 2003 Cygnal Integrated Products, Inc. DS010-1.0 APR03
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