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PDF TC500 Data sheet ( Hoja de datos )

Número de pieza TC500
Descripción (TC5xx) PRECISION ANALOG FRONT ENDS
Fabricantes TelCom Semiconductor 
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( DataSheet : www.DataSheet4U.com )
PRECISION ANALOG FRONT ENDS
PRECISION ANALOG FRONT ENDS
EVALUATION
KIT
AVAILABLE
TTCC55000
TTCC550000A
TTCC55110
TTCC55114
FEATURES
s Precision (up to 17 Bits) A/D Converter "Front End"
s 3-Pin Control Interface to Microprocessor
s Flexible: User Can Trade-Off Conversion Speed
for Resolution
s Single Supply Operation (TC510/514)
s 4 Input, Differential Analog MUX (TC514)
s Automatic Input Voltage Polarity Detection
s Low Power Dissipation ........... TC500/500A: 10mW
TC510/514: 18mW
s Wide Analog Input Range ....... ±4.2V (TC500A/510)
s Directly Accepts Bipolar and Differential Input
Signals
ORDERING INFORMATION
Part No.
TC500ACOE
TC500ACPE
TC500COE
TC500CPE
TC510COG
TC510CPF
TC514COI
TC514CPJ
TC500EV
Package
Temp. Range
16-Pin SOIC
0°C to +70°C
16-Pin Plastic DIP (Narrow) 0°C to +70°C
16-Pin SOIC
0°C to +70°C
16-Pin Plastic DIP (Narrow) 0°C to +70°C
24-Pin SOIC
0°C to +70°C
24-Pin Plastic DIP (300 Mil.) 0°C to +70°C
28-Pin SOIC
0°C to +70°C
28-Pin Plastic DIP (300 Mil.) 0°C to +70°C
Evaluation Kit for TC500/500A/510/514
GENERAL DESCRIPTION
The TC500/500A/510/514 family are precision analog
front ends that implement dual slope A/D converters having
a maximum resolution of 17 bits plus sign. As a minimum,
each device contains the integrator, zero crossing compara-
tor and processor interface logic. The TC500 is the base
(16 bit max) device and requires both positive and negative
power supplies. The TC500A is identical to the TC500,
except it has improved linearity allowing it to operate to a
maximum resolution of 17 bits. The TC510 adds an on-
board negative power supply converter for single supply
operation. The TC514 adds both a negative power supply
converter and a 4 input differential analog multiplexer.
Each device has the same processor control interface
consisting of 3 wires: control inputs A and B and zero-
crossing comparator output (CMPTR). The processor ma-
nipulates A, B to sequence the TC5xx through four phases
of conversion: Auto Zero, Integrate, Deintegrate and Inte-
grator Zero. During the Auto Zero phase, offset voltages in
the TC5xx are corrected by a closed-loop feedback mecha-
nism. The input voltage is applied to the integrator during the
Integrate phase. This causes an integrator output dv/dt
directly proportional to the magnitude of the input voltage.
The higher the input voltage, the greater the magnitude of
the voltage stored on the integrator during this phase. At the
start of the Deintegrate phase, an external voltage reference
is applied to the integrator, and at the same time, the external
host processor starts its on-board timer. The processor
FUNCTIONAL BLOCK DIAGRAM
CH1 +
CH2 +
CH3 +
CH4 +
CH1
CH2
CH3
CH4
ACOM
VS
OSC
A0 A1
DIF.
MUX
(TC514)
CR+EF
CREF
VR+EF
VR–EF
CR–EF
RINT
CINT
CAZ
BUF CAZ
CINT
A
0
0
1
1
CONTROL LOGIC
B CONVERTER STATE
0 ZERO INTEGRATOR OUTPUT
1 AUTO-ZERO
0 SIGNAL INTEGRATE
1 DEINTEGRATE
SWR SWR
SWI
SWR–I SWR+I
BUFFER
+
INTEGRATOR
CMPTR 1
+
+
TC500
TC500A
TC510
CMPTR 2 TC514
LEVEL
+ SHIFT
CMPTR
OUTPUT
SWZ
SWR+I SWR–I
SWIZ SWZ
POLARITY
DETECTION
SW1
SWI
DC-TO-DC
CONVERTER
(TC510 & TC514)
ANALOG
SWITCH
CONTROL
SIGNALS
VO–UT CAP– CAP+
PHASE
DECODING
LOGIC
DGND
1.0µF
CO–UT
1.0µF
VSS
(TC500
TC500A)
AB
CONTROL LOGIC
TC500/A/510/514-3 10/3/96 TelCom Semiconductor reserves the right to make changes in the circuitry1and specifications of its devices.
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1 page




TC500 pdf
PRECISION ANALOG FRONT ENDS
TC500
TC500A
TC510
TC514
PIN DESCRIPTION
Pin No. Pin No.
(TC500, 500A) (TC510)
12
2 Not Used
33
44
55
66
77
88
99
10 15
11 16
12 18
13 17
14 19
15 23
16 21
22
24
1
20
Pin No.
(TC514)
2
Not Used
3
4
5
6
7
8
9
Not Used
Not Used
22
21
23
27
25
26
28
1
24
18
13
17
12
16
11
15
Symbol Description
CINT
VSS
CAZ
BUF
ACOM
CR–EF
CR+ EF
VR– EF
VR+ EF
VI–N
VI+N
A
B
CMPTR OUT
DGND
VDD
CAP+
CAP–
VO– UT
OSC
CH1+
CH1
CH2+
CH2
CH3+
CH3
CH4+
Integrator output. Integrator capacitor connection.
Negative power supply input (TC500/500A only).
Auto-zero input. The Auto-zero capacitor connection.
Buffer output. The Integrator capacitor connection.
This pin is grounded in most applications. It is recommended that
ACOM and the input common pin (VI–N or C–HN ) be within the
analog common mode range (CMR).
Input. Negative reference capacitor connection.
Input. Positive reference capacitor connection.
Input. External voltage reference (–) connection.
Input. External voltage reference (+) connection.
Negative analog input.
Positive analog input.
Input. Converter phase control MSB. (See input B.)
Input. Converter phase control LSB. The states of A, B place the
TC5xx in one of four required phases. A conversion is complete
when all four phases have been executed:
00: Integrator Zero
Phase control input pins: AB =
01: Auto Zero
10: Integrate
11: Deintegrate
Zero crossing comparator output. CMPTR is HIGH during the
Integration phase when a positive input voltage is being integrated
and is LOW when a negative input voltage is being integrated. A
HIGH-to-LOW transition on CMPTR signals the processor that the
Deintegrate phase is completed. CMPTR is undefined during the
Auto-Zero phase. It should be monitored to time the Integrator Zero
phase (see text).
Input. Digital ground.
Input. Power supply positive connection.
Input. Negative power supply converter capacitor (+) connection.
Input. Negative power supply converter capacitor (–) connection.
Output. Negative power supply converter output and reservoir
capacitor connection. This output can be used to power other
devices in the circuit requiring a negative bias voltage.
Oscillator control input. The negative power supply converter normally
runs at a frequency of 100kHz. The converter oscillator frequency can
be slowed down (to reduce quiescent current) by connecting an
external capacitor between this pin and VDD. (See Typical Character-
istics Curves).
Positive analog input pin. MUX channel 1.
Negative analog input pin. MUX channel 1.
Positive analog input pin. MUX channel 2.
Negative analog input pin. MUX channel 2.
Positive analog input pin. MUX channel 3.
Negative analog input pin. MUX channel 3.
Positive analog input pin. MUX channel 4.
5

5 Page





TC500 arduino
PRECISION ANALOG FRONT ENDS
S
S
30 µV
TC500
TC500A
TC510
TC514
S
N
TH
N
TH
N
TH
Low
REF
INTEGRATOR
OUTPUT
Normal
V
REF
SLOPE (S) = VREF
RINT CINT
NTH = Noise Threshold
High
V
REF
Figure 6. Noise
ZERO
CROSSING
OVERSHOOT
Figure 8 shows the overall timing for a typical system in
which a TC5xx is interfaced to a microcontroller. The
microcontroller drives the A, B inputs with I/O lines and
monitors the comparator output, CMPTR, using an I/O line
or dedicated timer-capture control pin. It may be necessary
to monitor the state of the CMPTR output in addition to
having it control a timer directly for the Reference Deintegra-
tion phase. (This is further explained below.)
The timing diagram in Figure 8 is not to scale as the
timing in a real system depends on many system parameters
COMPARATOR
OUTPUT COMP
and component value selections. There are four critical
timing events (as shown in Figure 8): sampling the input
DEINTEGRATE PHASE
polarity; capturing the deintegration time; minimizing over-
INTEGRATE
INTEGRATOR
shoot and properly executing the Integrator Output Zero
PHASE
ZERO PHASE
phase.
Figure 7. Overshoot
DESIGN CONSIDERATIONS
Noise
The threshold noise (NTH) is the algebraic sum of the
integrator noise and the comparator noise. This value is
typically 30µV. Figure 6 shows how the value of the refer-
ence voltage can affect the final count. Such errors can be
reduced by increased integration times, in the same way
that 50/60Hz noise is rejected. The signal-to-noise ratio is
related to the integration time (tINT) and the integration time
constant (RINT) (CINT) as follows:
Auto-Zero Phase
The length of this phase is usually set to be equal to the
Input Signal Integration time. This decision is virtually arbi-
trary since the magnitudes of the various system errors are
not known. Setting the Auto-Zero time equal to the Input
Integrate time should be more than adequate to null out
system errors. The system may remain in this phase indefi-
nitely, i.e., Auto-Zero is the appropriate idle state for a TC5xx
device.
Input Signal Integrate Phase
( )S/N (dB) = 20 Log
VIN
30 x 10–6
tINT
(RINT) • (CINT)
System Timing
To obtain maximum performance from the TC5xx, the
overshoot at the end of the Deintegration phase must be
minimized. Also, the Auto Zero phase must be terminated as
soon as the comparator output returns high. (See timing
diagram, Figure 8).
The length of this phase is constant from one conversion
to the next and depends on system parameters and compo-
nent value selections. The calculation of tINT is shown
elsewhere in this data sheet. At some point near the end of
this phase, the microcontroller should sample CMPTR to
determine the input signal polarity. This value is, in effect,
the Sign Bit for the overall conversion result. Optimally,
CMPTR should be sampled just before this phase is termi-
nated by changing AB from 10 to 11. The consideration here
11

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