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PDF 16C550 Data sheet ( Hoja de datos )
| Número de pieza | 16C550 | |
| Descripción | TL16C550 | |
| Fabricantes | ETC | |
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TL16C550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS057D – AUGUST 1989 – REVISED MARCH 1996
D Capable of Running With All Existing
TL16C450 Software
D After Reset, All Registers Are Identical to
the TL16C450 Register Set
D In the FIFO Mode, Transmitter and Receiver
Are Each Buffered With 16-Byte FIFOs to
Reduce the Number of Interrupts to the
CPU
D In the TL16C450 Mode, Holding and Shift
Registers Eliminate the Need for Precise
Synchronization Between the CPU and
www.DataSheet4U.com Serial Data
D Programmable Baud Rate Generator Allows
Division of Any Input Reference Clock by 1
to (216 – 1) and Generates an Internal 16×
Clock
D Standard Asynchronous Communication
Bits (Start, Stop, and Parity) Added to or
Deleted From the Serial Data Stream
D Independent Receiver Clock Input
D Transmit, Receive, Line Status, and Data
Set Interrupts Independently Controlled
D Fully Programmable Serial Interface
Characteristics:
– 5-, 6-, 7-, or 8-Bit Characters
– Even-, Odd-, or No-Parity Bit Generation
and Detection
– 1-, 1 1/2-, or 2-Stop Bit Generation
– Baud Generation (dc to 256 Kbit/s)
D False-Start Bit Detection
D Complete Status Reporting Capabilities
D 3-State TTL Drive Capabilities for
Bidirectional Data Bus and Control Bus
D Line Break Generation and Detection
D Internal Diagnostic Capabilities:
– Loopback Controls for Communications
Link Fault Isolation
– Break, Parity, Overrun, Framing Error
Simulation
D Fully Prioritized Interrupt System Controls
D Modem Control Functions (CTS, RTS, DSR,
DTR, RI, and DCD)
D Faster Plug-In Replacement for National
Semiconductor NS16550A
description
The TL16C550A is a functional upgrade of the TL16C450 asynchronous communications element (ACE).
Functionally identical to the TL16C450 on power up (character mode†), the TL16C550A can be placed in an
alternate mode (FIFO) to relieve the CPU of excessive software overhead.
In this mode, internal FIFOs are activated allowing 16 bytes (plus 3 bits of error data per byte in the receiver
FIFO) to be stored in both receive and transmit modes. To minimize system overhead and maximize system
efficiency, all logic is on the chip. Two of the TL16C450 terminal functions (terminals 24 and 29 on the N package
and terminals 27 and 32 on the FN package) have been changed to allow signalling of direct memory address
(DMA) transfers.
The TL16C550A performs serial-to-parallel conversion on data received from a peripheral device or modem
and parallel-to-serial conversion on data received from its CPU. The CPU can read and report on the status of
the ACE at any point in the ACE’s operation. Reported status information includes the type of transfer operation
in progress, the status of the operation, and any error conditions encountered.
The TL16C550A ACE includes a programmable, on-board, baud rate generator. This generator is capable of
dividing a reference clock input by divisors from 1 to (216 – 1) and producing a 16 × clock for driving the internal
transmitter logic. Provisions are included to use this 16× clock to drive the receiver logic. Also included in the
ACE is a complete modem control capability and a processor interrupt system that may be software tailored
to the user’s requirements to minimize the computing required to handle the communications link.
† The TL16C550A can also be reset to the TL16C450 mode under software control.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
•POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright © 1996, Texas Instruments Incorporated
1
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TL16C550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS057D – AUGUST 1989 – REVISED MARCH 1996
Terminal Functions (continued)
TERMINAL
NAME
NO.† I/O
DESCRIPTION
RI 39 [43] I Ring indicator. RI is a modem status signal. Its condition can be checked by reading bit 6 (RI) of the modem status
register. Bit 2 (TERI) of the modem status register indicates that the RI input has transitioned from a low to a high
state since the last read from the modem status register. If the modem status interrupt is enabled when this transition
occurs, an interrupt is generated.
RTS 32 [36] O Request to send. When active, RTS informs the modem or data set that the ACE is ready to transmit data. RTS
is set to its active state by setting the RTS modem control register bit, and is set to its inactive (high) state either
as a result of a master reset or during loop mode operations or by clearing bit 1 (RTS) of the modem control register.
RXRDY
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29 [32] O Receiver ready output. Receiver direct memory access (DMA) signalling is available with RXRDY. When operating
in the FIFO mode, one of two types of DMA signalling can be selected with FCR3. When operating in the TL16C450
mode, only DMA mode 0 is allowed. Mode 0 supports single-transfer DMA in which a transfer is made between
CPU bus cycles. Mode 1 supports multitransfer DMA in which multiple transfers are made continuously until the
receiver FIFO has been emptied. In DMA mode 0 (FCR0 = 0 or FCR0 = 1, FCR3 = 0), if there is at least 1 character
in the receiver FIFO or receiver holding register, RXRDY is active (low). When RXRDY has been active but there
are no characters in the FIFO or holding register, RXRDY goes inactive (high). In DMA mode 1 (FCR0 = 1, FCR3
= 1), when the trigger level or the timeout has been reached, RXRDY goes active (low); when it has been active
but there are no more characters in the FIFO or holding register, it goes inactive (high).
SIN 10 [11] I Serial input. SIN is a serial data input from a connected communications device.
SOUT
11 [13] O Serial output. SOUT is a composite serial data output to a connected communication device. SOUT is set to the
marking (high) state as a result of master reset.
TXRDY
24 [27] O Transmitter ready output. Transmitter DMA signalling is available with TXRDY. When operating in the FIFO mode,
one of two types of DMA signalling can be selected with FCR3. When operating in the TL16C450 mode, only DMA
mode 0 is allowed. Mode 0 supports single-transfer DMA in which a transfer is made between CPU bus cycles.
Mode 1 supports multitransfer DMA in which multiple transfers are made continuously until the transmit FIFO has
been filled.
VCC
VSS
WR1
WR2
40 [44]
5-V supply voltage
20 [22]
Supply common
18 [20] I Write inputs. When either WR1 or WR2 are active (high or low respectively) while the ACE is selected, the CPU
19 [21]
is allowed to write control words or data into a selected ACE register. Only one of these inputs is required to transfer
data during a write operation; the other input should be tied in its inactive state (i.e., WR2 tied low or WR1 tied high).
XIN 16 [18] I/O External clock. XIN and XOUT connect the ACE to the main timing reference (clock or crystal).
XOUT
17 [19]
† Terminal numbers shown in brackets are for the FN package.
•POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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5 Page 
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TL16C550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS057D – AUGUST 1989 – REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
ADS
50%
tw5
50%
50%
A0 – A2 50%
tsu1
Valid
th1
50% Valid† 50%
CS0, CS1, CS2
50%
Valid
tsu2
th2
50% Valid†
50%
RD1, RD2
td7†
td8†
50%
th6
tw7
Active
th7†
td9
50%
DDIS
tdis(R)
50%
tdis(R)
50%
td10
td11
D7 – D0
Valid Data
† Applicable only when ADS is tied low.
Figure 3. Read Cycle Timing Waveforms
•POST OFFICE BOX 655303 DALLAS, TEXAS 75265
11
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