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PDF KM644002B Data sheet ( Hoja de datos )
| Número de pieza | KM644002B | |
| Descripción | 1M X 4 Bit (with Oe)high Speed CMOS Static RAM | |
| Fabricantes | Samsung Semiconductor | |
| Logotipo |  |
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( DataSheet : www.DataSheet4U.com )
KM644002B, KM644002BI
PRELIMINARY
CMOS SRAM
Document Title
1Mx4 Bit (with OE) High Speed Static RAM(5V Operating),
Operated at Commercial and Industrial Temperature Range.
Revision History
RevNo.
Rev. 0.0
Rev.1.0
Rev. 2.0
Rev.2.1
History
Initial release with Design Target.
Release to Preliminary Data Sheet.
1. Replace Design Target to Preliminary.
Release to Final Data Sheet
1. Delete Preliminary
2. Add 30pF capacitive in test load
3. Relex DC characteristics
Item
ICC 10ns
12ns
15ns
ISB f=max.
Previous
190mA
180mA
170mA
40mA
Current
195mA
190mA
185mA
50mA
Change operating current at Industrial Temperature range.
Previous spec.
Changed spec.
Items
(10/12/15ns part)
(10/12/15ns part)
ICC
195/190/185mA
220/215/210mA
Draft Data
Jan. 1st 1997
Jun. 1st 1997
Remark
Design Target
Preliminary
Feb. 11th 1998 Final
Jun. 27th 1998 Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-1-
Rev 2.1
June 1998
www.DataSheet4U.com
www.DataSheet4U.com
1 page  
KM644002B, KM644002BI
WRITE CYCLE
Parameter
Symbol
KM644002B-10
Min Max
Write Cycle Time
Chip Select to End of Write
Address Set-up Time
Address Valid to End of Write
Write Pulse Width(OE High)
Write Pulse Width(OE Low)
Write Recovery Time
Write to Output High-Z
Data to Write Time Overlap
Data Hold from Write Time
End Write to Output Low-Z
tWC
tCW
tAS
tAW
tWP
tWP1
tWR
tWHZ
tDW
tDH
tOW
10
7
0
7
7
10
0
0
5
0
3
-
-
-
-
-
-
-
5
-
-
-
NOTE: The above parameters are also guaranteed at industrial temperature range.
PRELIMINARY
CMOS SRAM
KM644002B-12
Min Max
12 -
8-
0-
8-
8-
12 -
0-
06
6-
0-
3-
KM644002B-15
Min Max
15 -
10 -
0-
10 -
10 -
15 -
0-
07
7-
0-
3-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH)
Address
Data Out
tOH
Previous Valid Data
tAA
tRC
Valid Data
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
Address
CS
OE
Data out
VCC
Current
ICC
ISB
tAA
tCO
tOE
tOLZ
tLZ(4,5)
tPU
50%
tRC
tHZ(3,4,5)
tOHZ
Valid Data
tOH
tPD
50%
-5-
Rev 2.1
June 1998
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet KM644002B.PDF ] | |
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