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PDF TC59LM905AMB Data sheet ( Hoja de datos )
| Número de pieza | TC59LM905AMB | |
| Descripción | (TC59LM905AMB / TC59LM913AMB) Network FCRAM | |
| Fabricantes | Toshiba Semiconductor | |
| Logotipo |  |
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( DataSheet : www.DataSheet4U.com )
TC59LM913/05AMB-50,-55,-60
TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC
8,388,608-WORDS × 4 BANKS × 16-BITS Network FCRAMTM
16,777,216-WORDS × 4 BANKS × 8-BITS Network FCRAMTM
DESCRIPTION
Network FCRAMTM is Double Data Rate Fast Cycle Random Access Memory. TC59LM913/05AMB is Network
FCRAMTM containing 536,870,912 memory cells. TC59LM913AMB is organized as 8,388,608-words × 4 banks × 16
bits, TC59LM905AMB is organized as 16,777,216-words × 4 banks × 8 bits. TC59LM913/05AMB feature a fully
synchronous operation referenced to clock edge whereby all operations are synchronized at a clock input which
enables high performance and simple user interface coexistence. TC59LM913/05AMB can operate fast core cycle
compared with regular DDR SDRAM.
TC59LM913/05AMB is suitable for Network, Server and other applications where large memory density and low
power consumption are required. The Output Driver for Network FCRAMTM is capable of high quality fast data
transfer under light loading condition.
FEATURES
PARAMETER
TC59LM913/05
-50 -55 -60
tCK Clock Cycle Time (min)
CL = 3
CL = 4
5.5 ns
5.0 ns
6.0 ns
5.5 ns
6.5 ns
6.0 ns
tRC Random Read/Write Cycle Time (min)
25.0 ns
27.5 ns
30.0 ns
tRAC Random Access Time (max)
22.0 ns
24.0 ns
26.0 ns
IDD1S Operating Current (single bank) (max)
TBD
TBD
TBD
lDD2P Power Down Current (max)
TBD
TBD
TBD
lDD6 Self-Refresh Current (max)
TBD
TBD
TBD
• Fully Synchronous Operation
• Double Data Rate (DDR)
Data input/output are synchronized with both edges of DQS.
• Differential Clock (CLK and CLK ) inputs
CS , FN and all address input signals are sampled on the positive edge of CLK.
Output data (DQs and DQS) is aligned to the crossings of CLK and CLK .
• Fast clock cycle time of 5 ns minimum
Clock: 200 MHz maximum
Data: 400 Mbps/pin maximum
• Fast cycle and Short Latency
• Distributed Auto-Refresh cycle in 7.8 µs
• Self-Refresh
• Power Down Mode
• Variable Write Length Control
• Write Latency = CAS Latency-1
• Programable CAS Latency and Burst Length
CAS Latency = 3, 4
Burst Length = 2, 4
• Organization: TC59LM813AMB : 8,388,608 words × 4 banks × 16 bits
TC59LM805AMB : 16,777,216 words × 4 banks × 8 bits
• Power Supply Voltage VDD: 2.5 V ± 0.15V
VDDQ: 2.5 V ± 0.15 V
• 2.5 V CMOS I/O comply with SSTL-2 (half strength driver)
• Package:
60Ball BGA, 1mm × 1mm Ball pitch
Notice : FCRAM is trademark of Fujitsu Limited, Japan.
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2003-04-21 1/49
1 page  
ABSOLUTE MAXIMUM RATINGS
TC59LM913/05AMB-50,-55,-60
SYMBOL
PARAMETER
RATING
UNIT
NOTES
VDD Power Supply Voltage
−0.3~3.3
V
VDDQ
Power Supply Voltage (for I/O buffer)
−0.3~VDD+ 0.3
V
VIN Input Voltage
−0.3~VDD+ 0.3
V
VOUT
Output and I/O pin Voltage
−0.3~VDDQ + 0.3
V
VREF
Input Reference Voltage
−0.3~VDD+ 0.3
V
Topr Operating Temperature (Ambient)
0~70
°C
Tstg Storage Temperature
−55~150
°C
Tsolder
Soldering Temperature (10 s)
260 °C
PD Power Dissipation
2W
IOUT
Short Circuit Output Current
±50 mA
Caution: Conditions outside the limits listed under “ABSOLUTE MAXIMUM RATINGS” may cause permanent damage to the device.
The device is not meant to be operated under conditions outside the limits described in the operational section of this
specification.
Exposure to “ABSOLUTE MAXIMUM RATINGS” conditions for extended periods may affect device reliability.
RECOMMENDED DC, AC OPERATING CONDITIONS (Notes: 1)(TCASE = 0~85°C)
SYMBOL
PARAMETER
MIN
VDD
VDDQ
VREF
VIH (DC)
VIL (DC)
VICK (DC)
VID (DC)
VIH (AC)
VIL (AC)
VID (AC)
VX (AC)
VISO (AC)
Power Supply Voltage
2.35
Power Supply Voltage (for I/O buffer)
2.35
Input Reference Voltage
Input DC High Voltage
Input DC Low Voltage
VDDQ/2 × 96%
VREF + 0.2
−0.1
Differential Clock DC Input Voltage
−0.1
Input Differential Voltage.
CLK and CLK inputs (DC)
0.4
Input AC High Voltage
Input AC Low Voltage
VREF + 0.35
−0.1
Input Differential Voltage.
CLK and CLK inputs (AC)
0.7
Differential AC Input Cross Point Voltage
Differential Clock AC Middle Level
VDDQ/2 − 0.2
VDDQ/2 − 0.2
TYP.
2.5
VDD
VDDQ/2
MAX
UNIT NOTES
2.65
VDD
VDDQ/2 × 104%
VDDQ + 0.2
VREF − 0.2
VDDQ + 0.1
V
V
V
V
V
V
2
5
5
10
VDDQ + 0.2 V 7, 10
VDDQ + 0.2
VREF − 0.35
V
V
3, 6
4, 6
VDDQ + 0.2 V 7, 10
VDDQ/2 + 0.2
VDDQ/2 + 0.2
V
V
8, 10
9, 10
2003-04-21 5/49
5 Page 
POWER UP SEQUENCE
TC59LM913/05AMB-50,-55,-60
(1) As for PD , being maintained by the low state (≤ 0.2 V) is desirable before a power-supply injection.
(2) Apply VDD before or at the same time as VDDQ.
(3) Apply VDDQ before or at the same time as VREF.
(4) Start clock (CLK, CLK ) and maintain stable condition for 200 µs (min).
(5) After stable power and clock, apply DESL and take PD =H.
(6) Issue EMRS to enable DLL and to define driver strength. (Note: 1)
(7) Issue MRS for set CAS latency (CL), Burst Type (BT), and Burst Length (BL). (Note: 1)
(8) Issue two or more Auto-Refresh commands (Note: 1).
(9) Ready for normal operation after 200 clocks from Extended Mode Register programming.
Notes:
(1)
(2)
Sequence 6, 7 and 8 can be issued in random order.
L = Logic Low, H = Logic High
VDD
VDDQ
VREF
2.5V(TYP)
2.5V(TYP)
1.25V(TYP)
CLK
CLK
PD
tPDEX
200us(min)
lPDA
lRSC
lRSC
lREFC
200clock cycle(min)
lREFC
Command
Address
DQ
DQS
DESL RDA MRS DESL RDA MRS DESL WRA REF DESL
op-code
op-code
WRA REF DESL
EMRS
MRS
Hi-Z
EMRS
MRS
Auto Refresh cycle
Normal Operation
2003-04-21 11/49
11 Page | ||
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| PDF Descargar | [ Datasheet TC59LM905AMB.PDF ] | |
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