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PDF TC59LM836DMB Data sheet ( Hoja de datos )
| Número de pieza | TC59LM836DMB | |
| Descripción | Network FCRAM | |
| Fabricantes | Toshiba Semiconductor | |
| Logotipo |  |
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( DataSheet : www.DataSheet4U.com )
TC59LM836DMB-30,-33,-40
TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC
2,097,152-WORDS × 4 BANKS × 36-BITS Network FCRAMTM
DESCRIPTION
Network FCRAMTM is Double Data Rate Fast Cycle Random Access Memory. TC59LM836DMB is Network
FCRAMTM containing 301,989,888 memory cells. TC59LM836DMB is organized as 2,097,152-words × 4 banks × 36
bits. TC59LM836DMB feature a fully synchronous operation referenced to clock edge whereby all operations are
synchronized at a clock input which enables high performance and simple user interface coexistence.
TC59LM836DMB can operate fast core cycle compared with regular DDR SDRAM.
TC59LM836DMB is suitable for Network and other applications where large memory density and low power
consumption are required. The Output Driver for Network FCRAMTM is capable of high quality fast data transfer
under light loading condition.
FEATURES
PARAMETER
TC59LM836DMB
-30 -33
CL = 4
4.0 ns
4.5 ns
tCK Clock Cycle Time (min)
CL = 5
3.33 ns
3.75 ns
CL = 6
3.0 ns
3.33 ns
tRC Random Read/Write Cycle Time (min)
20.0 ns
22.5 ns
tRAC Random Access Time (max)
20.0 ns
22.5 ns
IDD1S Operating Current (single bank) (max)
380 mA
360 mA
lDD2P Power Down Current (max)
80 mA
75 mA
lDD6 Self-Refresh Current (max)
10 mA
10 mA
• Fully Synchronous Operation
• Double Data Rate (DDR)
Data input/output are synchronized with both edges of DS / QS.
• Differential Clock (CLK and CLK ) inputs
CS , FN and all address input signals are sampled on the positive edge of CLK.
Output data (DQs and QS) is aligned to the crossings of CLK and CLK .
• Fast clock cycle time of 3.0 ns minimum
Clock: 333 MHz maximum
Data: 666 Mbps/pin maximum
• Quad Independent Banks operation
• Fast cycle and Short Latency
• Selectable Data Strobe
• Distributed Auto-Refresh cycle in 3.9 µs
• Self-Refresh
• Power Down Mode
• Variable Write Length Control
• Write Latency = CAS Latency-1
• Programable CAS Latency and Burst Length
CAS Latency = 4, 5, 6
Burst Length = 2, 4
• Organization: 2,097,152 words × 4 banks × 36 bits
• Power Supply Voltage VDD: 2.5 V ± 0.125V
VDDQ: 1.4 V ~ 1.9 V
• Low voltage CMOS I/O covered with SSTL-18 (Half strength driver) and HSTL.
• JTAG boundary scan
• Package: 144Ball BGA, 1mm × 0.8mm Ball pitch (P-TFBGA144-1119-0.80AZ)
-40
5.0 ns
4.5 ns
4.0 ns
25 ns
25 ns
340 mA
70 mA
10 mA
Notice: FCRAM is trademark of Fujitsu limited, Japan.
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2003-03-12 1/63
1 page  
ABSOLUTE MAXIMUM RATINGS
TC59LM836DMB-30,-33,-40
SYMBOL
PARAMETER
RATING
UNIT
NOTES
VDD Power Supply Voltage
−0.3~ 3.3
V
VDDQ
Power Supply Voltage (for DQ buffer)
−0.3~VDD+ 0.3
V
VIN Input Voltage
−0.3~VDD+ 0.3
V
VOUT
Output and DQ pin Voltage
−0.3~VDDQ + 0.3
V
VREF
Input Reference Voltage
−0.3~VDD+ 0.3
V
Topr Operating Temperature (Ambient)
0~70
°C
Tstg Storage Temperature
−55~150
°C
Tsolder
Soldering Temperature (10 s)
260 °C
PD Power Dissipation
2W
IOUT
Short Circuit Output Current
±50 mA
Caution: Conditions outside the limits listed under “ABSOLUTE MAXIMUM RATINGS” may cause permanent damage to the device.
The device is not meant to be operated under conditions outside the limits described in the operational section of this
specification.
Exposure to “ABSOLUTE MAXIMUM RATINGS” conditions for extended periods may affect device reliability.
RECOMMENDED DC, AC OPERATING CONDITIONS (Notes: 1)(TCASE = 0~85°C)
SYMBOL
PARAMETER
MIN
VDD
VDDQ
VREF
VIH (DC)
VIL (DC)
VICK (DC)
VID (DC)
VIH (AC)
VIL (AC)
VID (AC)
VX (AC)
VISO (AC)
Power Supply Voltage
2.375
Power Supply Voltage (for DQ buffer)
1.4
Reference Voltage
Input DC High Voltage
Input DC Low Voltage
VDDQ/2 × 95%
VREF + 0.125
−0.1
Differential Clock DC Input Voltage
−0.1
Differential Input Voltage.
CLK and CLK inputs (DC)
0.4
Input AC High Voltage
Input AC Low Voltage
VREF + 0.2
−0.1
Differential Input Voltage.
CLK and CLK inputs (AC)
0.55
Differential AC Input Cross Point Voltage VDDQ/2 − 0.125
Differential Clock AC Middle Level
VDDQ/2 − 0.125
TYP.
2.5
VDDQ/2
MAX
UNIT NOTES
2.625
1.9
VDDQ/2 × 105%
VDDQ + 0.2
VREF − 0.125
VDDQ + 0.1
V
V
V
V
V
V
2
5
5
10
VDDQ + 0.2 V 7, 10
VDDQ + 0.2 V 3, 6
VREF − 0.2 V 4, 6
VDDQ + 0.2 V 7, 10
VDDQ/2 + 0.125
VDDQ/2 + 0.125
V
V
8, 10
9, 10
2003-03-12 5/63
5 Page 
POWER UP SEQUENCE
TC59LM836DMB-30,-33,-40
(1) As for PD , being maintained by the low state (≤ 0.2 V) is desirable before a power-supply injection.
(2) Apply VDD before or at the same time as VDDQ.
(3) Apply VDDQ before or at the same time as VREF.
(4) Start clock (CLK, CLK ) and maintain stable condition for 200 µs (min).
(5) After stable power and clock, apply DESL and take PD =H.
(6) Issue EMRS to enable DLL and to define driver strength and data strobe type. (Note: 1)
(7) Issue MRS for set CAS latency (CL), Burst Type (BT), and Burst Length (BL). (Note: 1)
(8) Issue two or more Auto-Refresh commands (Note: 1).
(9) Ready for normal operation after 200 clocks from Extended Mode Register programming.
Notes:
(1)
(2)
(3)
Sequence 6, 7 and 8 can be issued in random order.
L = Logic Low, H = Logic High
DQ output is Hi-Z state during power upsequence.
VDD
VDDQ
VREF
CLK
CLK
PD
2.5V(TYP)
1.5V or 1.8V(TYP)
1/2 VDDQ (TYP)
tPDEX
200us(min)
lPDA
lRSC
lRSC
lREFC
lLOCK = 200clock cycle(min)
lREFC
Command
Address
DQ
(Input)
DESL RDA MRS DESL RDA MRS DESL WRA REF DESL
op-code
op-code
WRA REF DESL
EMRS
MRS
DS
L/UQS
(Uni-QS mode)
L/UQS
(Free Running mode)
EMRS
MRS
Low
Auto Refresh cycle
Normal Operation
2003-03-12 11/63
11 Page | ||
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| PDF Descargar | [ Datasheet TC59LM836DMB.PDF ] | |
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