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PDF TC59LM818DMB Data sheet ( Hoja de datos )
| Número de pieza | TC59LM818DMB | |
| Descripción | Network FCRAM | |
| Fabricantes | Toshiba Semiconductor | |
| Logotipo |  |
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( DataSheet : www.DataSheet4U.com )
TC59LM818DMB-30,-33,-40
TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC
4,194,304-WORDS × 4 BANKS × 18-BITS Network FCRAMTM
DESCRIPTION
Network FCRAMTM is Double Data Rate Fast Cycle Random Access Memory. TC59LM818DMB is Network
FCRAMTM containing 301,989,888 memory cells. TC59LM818DMB is organized as 4,194,304-words × 4 banks × 18
bits. TC59LM818DMB feature a fully synchronous operation referenced to clock edge whereby all operations are
synchronized at a clock input which enables high performance and simple user interface coexistence.
TC59LM818DMB can operate fast core cycle compared with regular DDR SDRAM.
TC59LM818DMB is suitable for Network, Server and other applications where large memory density and low
power consumption are required. The Output Driver for Network FCRAMTM is capable of high quality fast data
transfer under light loading condition.
FEATURES
PARAMETER
TC59LM818DMB
-30 -33
CL = 4
4.0 ns
4.5 ns
tCK Clock Cycle Time (min)
CL = 5
3.33 ns
3.75 ns
CL = 6
3.0 ns
3.33 ns
tRC Random Read/Write Cycle Time (min)
20.0 ns
22.5 ns
tRAC Random Access Time (max)
20.0 ns
22.5 ns
IDD1S Operating Current (single bank) (max)
250 mA
235 mA
lDD2P Power Down Current (max)
60mA
55 mA
lDD6 Self-Refresh Current (max)
10 mA
10 mA
• Fully Synchronous Operation
• Double Data Rate (DDR)
Data input/output are synchronized with both edges of DS / QS.
• Differential Clock (CLK and CLK ) inputs
CS , FN and all address input signals are sampled on the positive edge of CLK.
Output data (DQs and QS) is aligned to the crossings of CLK and CLK .
• Fast clock cycle time of 3.0 ns minimum
Clock: 333 MHz maximum
Data: 666 Mbps/pin maximum
• Quad Independent Banks operation
• Fast cycle and Short Latency
• Selectable Data Strobe
• Distributed Auto-Refresh cycle in 3.9 µs
• Self-Refresh
• Power Down Mode
• Variable Write Length Control
• Write Latency = CAS Latency-1
• Programable CAS Latency and Burst Length
CAS Latency = 4, 5, 6
Burst Length = 2, 4
• Organization: 4,194,304 words × 4 banks × 18 bits
• Power Supply Voltage VDD: 2.5 V ± 0.125V
VDDQ: 1.4 V ~ 1.9 V
• Low voltage CMOS I/O covered with SSTL-18 (Half strength driver) and HSTL
• Package:
60Ball BGA, 1mm × 1mm Ball pitch (P-BGA60-0917-1.00AZ)
-40
5.0 ns
4.5 ns
4.0 ns
25 ns
25 ns
210 mA
50 mA
10 mA
Notice: FCRAM is trademark of Fujitsu limited, Japan.
www.DataSheet4U.com
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2003-02-28 1/55
1 page  
TC59LM818DMB-30,-33,-40
Note:
(1) All voltages referenced to VSS, VSSQ.
(2) VREF is expected to track variations in VDDQ DC level of the transmitting device.
Peak to peak AC noise on VREF may not exceed ±2% VREF (DC).
(3) Overshoot limit: VIH (max) = VDDQ + 0.7 V with a pulse width ≤ 5 ns.
(4) Undershoot limit: VIL (min) = −0.7 V with a pulse width ≤ 5 ns.
(5) VIH (DC) and VIL (DC) are levels to maintain the current logic state.
(6) VIH (AC) and VIL (AC) are levels to change to the new logic state.
(7) VID is differential voltage of CLK input level and CLK input level.
(8) The value of VX (AC) is expected to equal VDDQ/2 of the transmitting device.
(9) VISO means {VICK (CLK) + VICK ( CLK )} /2
(10) Refer to the figure below.
CLK
CLK
VSS
Vx
VICK
|VID (AC)|
Vx
VICK
Vx Vx Vx VID (AC)
VICK
VICK
0 V Differential
VISO
VSS
VISO (min)
VISO (max)
(11) In the case of external termination, VTT (termination voltage) should be gone in the range of VREF (DC) ±
0.04 V.
CAPACITANCE (VDD = 2.5V, VDDQ = 1.8 V, f = 1 MHz, Ta = 25°C)
SYMBOL
PARAMETER
CIN Input pin Capacitance
CINC
Clock pin (CLK, CLK ) Capacitance
CI/O DQ, DS, QS Capacitance
CNC
NC pin Capacitance
Note: These parameters are periodically sampled and not 100% tested.
MIN
1.5
1.5
2.5
MAX
2.5
2.5
3.5
1.5
Delta
0.25
0.25
0.5
UNIT
pF
pF
pF
pF
2003-02-28 5/55
5 Page 
TIMING DIAGRAMS
Input Timing
Command and Address
CLK
tCK
CLK
tIS tIH
CS 1st
tIS tIH
FN 1st
A0~A14
BA0, BA1
tIS tIH
UA, BA
tCK
tIS tIH
2nd
tIS tIH
2nd
tIS tIH
LA
Data
DS
DQn (input)
DQm (input)
tDS tDH
tDS tDH
tDS tDH
tDS tDH
Timing of the CLK, CLK
TC59LM818DMB-30,-33,-40
tCH tCL
Refer to the Command Truth Table.
CLK
CLK
tCH tCL
tT
tCK
VIH
VIH (AC)
VIL (AC)
VIL
tT
CLK
VIH
VID (AC)
CLK
VIL
VX VX VX
2003-02-28 11/55
11 Page | ||
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| PDF Descargar | [ Datasheet TC59LM818DMB.PDF ] | |
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